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freescale semiconductor data sheet: advance information document number: mpc5602p rev. 4.1, 09/2011 ? freescale semiconductor, inc., 2010-2011. all rights reserved. this document contains information on a product under development. freescale reserves the right to change or discontinue this product without notice. mpc5602p 64 lqfp (10 mm x 10 mm) 100 lqfp (14 mm x 14 mm) mpc5602p microcontroller data sheet ? up to 64 mhz, single issue, 32-bit cpu core complex (e200z0h) ? compliant with power architecture embedded category ? variable length encoding (vle) ? memory organization ? up to 256 kb on-chip code flash memory with ecc and erase/program controller ? optional: additional 64 (4 16) kb on-chip data flash memory with ecc for eeprom emulation ? up to 20 kb on-chip sram with ecc ? fail-safe protection ? programmable watchdog timer ? non-maskable interrupt ? fault collection unit ? nexus l1 interface ? interrupts and events ? 16-channel edma controller ? 16 priority level controller ? up to 25 external interrupts ? pit implements four 32-bit timers ? 120 interrupts are routed via intc ? general purpose i/os ? individually programmable as input, output or special function ? 37 on 64 lqfp ? 64 on 100 lqfp ? 1 general purpose etimer unit ? 6 timers each with up/down capabilities ? 16-bit resolution, cascadeable counters ? quadrature decode with rotation direction flag ? double buffer input capture and output compare ? communications interfaces ? up to 2 linflex modules (1 master/slave, 1 master only) ? up to 3 dspi channels with automatic chip select generation (up to 8/4/4 chip selects) ? 1 flexcan interface (2.0b active) with 32 message buffers ? 1 safety port based on flexcan with 32 message buffers and up to 8 mbit/s at 64 mhz capability usable as second can when not used as safety port ? one 10-bit analog-to-digital converter (adc) ? up to 16 input channels (16 ch on 100 lqfp and 12 ch on 64 lqfp) ? conversion time < 1 s including sampling time at full precision ? programmable cross triggering unit (ctu) ? 4 analog watchdogs with interrupt capability ? on-chip can/uart bootstrap loader with boot assist module (bam) ? 1 flexpwm unit ? 8 complementary or independent outputs with adc synchronization signals ? polarity control, reload unit ? integrated configurable dead time unit and inverter fault input pins ? 16-bit resolution ? lockable configuration ? clock generation ? 4?40 mhz main oscillator ? 16 mhz internal rc oscillator ? software-controlled fmpll capable of up to 64 mhz ? voltage supply ? 3.3 v or 5 v supply for i/os and adc ? on-chip single supply voltage regulator with external ballast transistor ? operating temperature ranges: ?40 to 125 c or ?40 to 105 c
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 2 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.5.1 high performance e200z0 core processor. . . . . .7 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . .8 1.5.3 enhanced direct memory access (edma) . . . . . .8 1.5.4 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.5.5 static random access memory (sram). . . . . . . .9 1.5.6 interrupt controller (intc) . . . . . . . . . . . . . . . . . .9 1.5.7 system status and configuration module (sscm)10 1.5.8 system clocks and clock generation . . . . . . . . .10 1.5.9 frequency-modulated phase-locked loop (fmpll) 10 1.5.10 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5.11 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . 11 1.5.12 periodic interrupt timer (pit) . . . . . . . . . . . . . . . 11 1.5.13 system timer module (stm) . . . . . . . . . . . . . . . 11 1.5.14 software watchdog timer (swt) . . . . . . . . . . . . 11 1.5.15 fault collection unit (fcu) . . . . . . . . . . . . . . . . .12 1.5.16 system integration unit ? lite (siul) . . . . . . . . .12 1.5.17 boot and censorship . . . . . . . . . . . . . . . . . . . . .12 1.5.18 error correction status module (ecsm). . . . . . .13 1.5.19 peripheral bridge (pbridge) . . . . . . . . . . . . . .13 1.5.20 controller area network (flexcan) . . . . . . . . . .13 1.5.21 safety port (flexcan) . . . . . . . . . . . . . . . . . . . .14 1.5.22 serial communication interface module (linflex)14 1.5.23 deserial serial peripheral interface (dspi) . . . .15 1.5.24 pulse width modulator (flexpwm) . . . . . . . . . .15 1.5.25 etimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.26 analog-to-digital converter (adc) module . . . . .17 1.5.27 cross triggering unit (ctu) . . . . . . . . . . . . . . . .17 1.5.28 nexus development interface (ndi) . . . . . . . . .18 1.5.29 cyclic redundancy check (crc) . . . . . . . . . . . .18 1.5.30 ieee 1149.1 jtag controller . . . . . . . . . . . . . . .19 1.5.31 on-chip voltage regulator (vreg). . . . . . . . . . .19 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . .19 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.2.1 power supply and reference voltage pins . . . . .21 2.2.2 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.2.3 pin multiplexing . . . . . . . . . . . . . . . . . . . . . . . . .23 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . 33 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 33 3.4 recommended operating conditions . . . . . . . . . . . . . . 36 3.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40 3.5.1 package thermal characteristics . . . . . . . . . . . 40 3.5.2 general notes for spec ifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . . 40 3.6 electromagnetic interference (emi) characteristics . . . 42 3.7 electrostatic discharge (esd) characteristics . . . . . . . 42 3.8 power management electrical characteristics . . . . . . . 42 3.8.1 voltage regulator electric al characteristics . . . . 42 3.8.2 voltage monitor electrical characteristics . . . . . 44 3.9 power up/down sequencing . . . . . . . . . . . . . . . . . . . . 44 3.10 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . 47 3.10.1 nvusro register . . . . . . . . . . . . . . . . . . . . . . . 47 3.10.2 dc electrical characteristics (5 v) . . . . . . . . . . 47 3.10.3 dc electrical characteristics (3.3 v) . . . . . . . . . 50 3.10.4 input dc electrical char acteristics definition . . 51 3.10.5 i/o pad current specification. . . . . . . . . . . . . . . 52 3.11 main oscillator electrical char acteristics . . . . . . . . . . . 53 3.12 fmpll electrical characteristics . . . . . . . . . . . . . . . . . 54 3.13 16 mhz rc oscillator electric al characteristics . . . . . . 56 3.14 analog-to-digital converter (a dc) electrical characteristics 56 3.14.1 input impedance and adc accuracy . . . . . . . . 57 3.14.2 adc conversion characteristics . . . . . . . . . . . . 62 3.15 flash memory electr ical characteristics. . . . . . . . . . . . 63 3.15.1 program/erase characteristics . . . . . . . . . . . . . 63 3.15.2 flash memory power supply dc characteristics64 3.15.3 start-up/switch-off timings . . . . . . . . . . . . . . . . 65 3.16 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.16.1 pad ac specifications . . . . . . . . . . . . . . . . . . . 65 3.17 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . 66 3.17.1 reset pin characteristics . . . . . . . . . . . . . . . . 66 3.17.2 ieee 1149.1 interface timing . . . . . . . . . . . . . . 69 3.17.3 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.17.4 external interrupt timing (irq pin) . . . . . . . . . . 73 3.17.5 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 80 4.1.1 100 lqfp mechanical outline drawing . . . . . . 80 4.1.2 64 lqfp mechanical outline drawing . . . . . . . 84 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 3 1 introduction 1.1 document overview this document provides electri cal specifications, pin assignmen ts, and package diagrams for the mpc5601p/2p series of microcontroller units (mcus). it also describes the devi ce features and highlights important electrical and physical characteristics. for functiona l characteristics, refer to the device reference manual. 1.2 description this 32-bit system-on-chip (soc) automotive microcontroller fa mily is the latest achievement in integrated automotive application controllers. it belongs to an expanding range of automotive-focused products designed to address chassis applications?specifically, electrical hydr aulic power steering (ehps) and electric pow er steering (eps)?as well as airbag applications. this family is one of a series of next -generation integrated automotive microcon trollers based on the power architecture ? technology. the advanced and cost-efficient host processor core of this au tomotive controller family complies with the power architecture embedded category. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infras tructure of current power arch itecture devices and is supported with software drivers, operating sy stems and configuration code to assist with users implementations. 1.3 device comparison table 1 provides a summary of different members of the mpc5602p family and their features to enable a comp arison among the family members and an understanding of the ra nge of functionality offered within this family. table 1. mpc5602p device comparison feature mpc5601p mpc5602p code flash memory (with ecc) 192 kb 256 kb data flash memory / ee option (with ecc) 64 kb (optional feature) sram (with ecc) 12 kb 20 kb processor core 32-bit e200z0h instruction set vle (variable length encoding) cpu performance 0?64 mhz fmpll (frequency-modulated phase-locked loop) module 1 intc (interrupt controller) channels 120 pit (periodic interrupt timer) 1 (with four 32-bit timers) edma (enhanced direct memory access) channels 16 flexcan (controller area network) 1 1,2 2 1,2 safety port yes (via flexcan module) yes (via second flexcan module) fcu (fault collection unit) yes ctu (cross triggering unit) no yes etimer 1 (16-bit, 6 channels)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 4 1.4 block diagram figure 1 shows a top-level block diagram of the mpc5602p mcu. table 2 summarizes the functions of the blocks. flexpwm (pulse-width modulation) channels no 8 (capture capability not supported) analog-to-digital converter (adc) 1 (10-bit, 16 channels) linflex 1 (1 master/slave) 2 (1 master/slave, 1 master only) dspi (deserial serial peripheral interface) 1 3 crc (cyclic redundancy check) unit yes junction temperature sensor no jtag controller yes nexus port controller (npc) yes (nexus l1+) supply digital power supply 3.3 v or 5 v single supply with external transistor analog power supply 3.3 v or 5 v internal rc oscillator 16 mhz external crystal oscillator 4?40 mhz packages 64 lqfp 100 lqfp temperature standard ambient temperature ?40 to 125 c 1 each flexcan module has 32 message buffers. 2 one flexcan module can act as a safety port with a bit rate as high as 8 mbit/s at 64 mhz. table 1. mpc5602p device comparison (continued) feature mpc5601p mpc5602p
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 5 figure 1. mpc5602p block diagram sram (with ecc) slave slave slave code flash (with ecc) data flash (with ecc) pit stm swt mc_rgm mc_cgm mc_me bam siul wkpu crc ecsm e200z0 core 32-bit general purpose registers special purpose registers integer execution unit exception handler variable length encoded instructions instruction unit load/store unit branch prediction unit jtag 1.2 v regulator control xosc 16 mhz rc oscillator fmpll_0 (system) nexus port controller interrupt controller edma 16 channels master master instruction 32-bit master data 32-bit crossbar switch (xbar, amba 2.0 v6 ahb) peripheral bridge fcu legend: adc analog-to-digital converter bam boot assist module crc cyclic redundancy check ctu cross triggering unit dspi deserial serial peripheral interface ecsm error correction status module edma enhanced direct memory access etimer enhanced timer fcu fault collection unit flash flash memory flexcan controller area network flexpwm flexible pulse width modulation fmpll frequency-modulated phase-locked loop intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module pit periodic interrupt timer siul system integration unit lite sram static random-access memory sscm system status and configuration module stm system timer module swt software watchdog timer wkpu wakeup unit xosc external oscillator xbar crossbar switch external ballast nexus 1 edma 16 channels flexpwm ctu 3 etimer dspi 2 flexcan linflex safety port adc (6 ch) sscm (10 bit, 16 ch)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 6 table 2. mpc5602p series block summary block function analog-to-digital converter (adc) multi-channel, 10-bit analog-to-digital converter boot assist module (bam) block of read-only memory co ntaining vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and control required fo r the generation of system and peripheral clocks controller area network (flexcan) support s the standard can communications protocol cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit crossbar switch (xbar) supports si multaneous connect ions between two master ports and three slave ports; supports a 32-bit address bus width and a 32-bit data bus width cyclic redundancy check ( crc) crc checksum generator deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels enhanced timer (etimer) provides enhanced programmable up/down modulo counting error correction status module (ecsm) provides a myriad of miscellaneous cont rol functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for ex iting sleep modes, and optional features such as information on memory errors reported by error-correcting codes external oscillator (xosc) provides an output clock us ed as input reference for fmpll_0 or as reference clock for specific modules depending on system needs fault collection unit (fcu) provides functional safety to the device flash memory provides non-volatile storage for program code, constants and variables frequency-modulated phase-locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation interrupt controller (intc) provides priority-b ased preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to syst em logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load mode entry module (mc_me) provides a mechanism for controlling the device oper ational mode and mode transition sequences in all functional stat es; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications periodic interrupt timer (pit) produces periodic interrupts and triggers peripheral bridge (pbridge) is the interface between the system bus and on-chip peripherals power control unit (mc_pcu) reduces the overall power co nsumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 7 1.5 feature details 1.5.1 high performance e200z0 core processor the e200z0 power architecture core provides the following features: ? high performance e200z0 core processor for managing peripherals and interrupts ? single issue 4-stage pipe line in-order execu tion 32-bit power architecture cpu ? harvard architecture ? variable length encoding (vle), allowing mixed 16- and 32-bit instructions ? results in smaller code size footprint ? minimizes impact on performance ? branch processing acceleration us ing lookahead instruction buffer ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? thirty-two 32-bit general purpose registers (gprs) ? separate instruction bus and load /store bus harvard architecture ? hardware vectored interrupt support ? reservation instructions for impl ementing read-modif y-write constructs ? long cycle time instructions, except for guarded loads, do not increase interrupt latency ? extensive system development support through nexus debug port ? non-maskable interrupt support pulse width modulator (flexpwm) contains four pwm submodu les, each of which capable of controlling a single half-bridge power stage and two fault input channels reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provi des control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with tr igger event configuration system status and configuration module (sscm) provides system configuration and status data (such as memory size and status, device mode and security status), devi ce identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar 1 and operating system tasks system watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) supports up to 18 external sources that can generat e interrupts or wakeup events, of which 1 can cause non-maskabl e interrupt requests or wakeup events 1 autosar: automotive open system archit ecture (see http://www.autosar.org) table 2. mpc5602p series block summary (continued) block function
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 8 1.5.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between three master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 32-bit data bus width. the crossbar allows for two concurrent tran sactions to occur from any master port to any slave port; but one of those transfers must be an instruction fetch from internal flash memory. if a slave port is simultaneously requ ested by more than one master port, arbitration logic will select the higher priority master and grant it ownership of the slave port. all other masters requ esting that slave port will be stalled until the higher priority ma ster completes its transactions. requesting masters will be treated with equal priority and will be granted access a slave port in round-robin fashion, based upon the id of the last master to be grant ed access. the crossbar provides the following features: ? 3 master ports: ? e200z0 core complex instruction port ? e200z0 core complex load/store data port ?edma ? 3 slave ports: ? flash memory (code and data) ?sram ? peripheral bridge ? 32-bit internal address, 32-bit internal data paths ? fixed priority arbitration based on port master ? temporary dynamic priori ty elevation of masters 1.5.3 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a s econd-generation modul e capable of performing complex data movements via 16 programmable channels, with minimal interventi on from the host processor. the hardware micro architecture includes a dma engine which performs source and destination ad dress calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control de scriptors (tcd) for the channels. the edma module provides the following features: ? 16 channels support independent 8-, 16- or 32-bit single value or block transfers ? supports variable-sized queues and circular queues ? source and destination address registers are independently configured to ei ther post-increment or to remain constant ? each transfer is initiated by a peri pheral, cpu, or edma channel request ? each edma channel can optionally send an interrupt requ est to the cpu on completion of a single value or block transfer ? dma transfers possible between system memo ries, dspis, adc, flexpwm, etimer and ctu ? programmable dma channel multiplexer allows assignment of any dma source to any available dma channel with as many as 30 request sources ? edma abort operation through software 1.5.4 flash memory the mpc5602p provides 320 kb of programmable, non-volatile, flash memory. the non-volatile memory (nvm) can be used for instruction and/or data storage. the flash memory module is interfaced to the system bus by a dedicated flash memory controller. it supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. the module contains four 128-bit wide prefetch buffers. prefetch buffer hits allow no-w ait responses. normal flash memory array accesses are registered and are forwarde d to the system bus on the following cycle, incurring two wait-states.
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 9 the flash memory module provid es the following features: ? as much as 320 kb flash memory ? 6 blocks (32 kb + 216 kb + 32 kb + 32 kb + 128 kb) code flash memory ? 4 blocks (16 kb + 16 kb + 16 kb + 16 kb) data flash memory ? full read-while-write (rww) capability between code flash memory and data flash memory ? four 128-bit wide prefetch buffers to provide single cycle in-line accesses (p refetch buffers can be configured to prefetch code or data or both) ? typical flash memory access time: no wait-state for buffer hits, 2 wait-sta tes for page buffer miss at 64 mhz ? hardware managed flash memory writes handled by 32-bit risc krypton engine ? hardware and software configur able read and write access prot ections on a per-master basis ? configurable access timing allowing use in a wide range of system frequencies ? multiple-mapping support and mapping- based block access timing (up to 31 additional cycles) allowing use for emulation of other memory types ? software programmable block progr am/erase restriction control ? erase of selected block(s) ? read page sizes ? code flash memory: 128 bits (4 words) ? data flash memory: 32 bits (1 word) ? ecc with single-bit correction, double-bit detection for data integrity ? code flash memory: 64-bit ecc ? data flash memory: 32-bit ecc ? embedded hardware program and erase algorithm ? erase suspend and program abort ? censorship protection scheme to prevent flash memory content visibility ? hardware support for eeprom emulation 1.5.5 static random access memory (sram) the mpc5602p sram module provides up to 20 kb of general-purpose memory. ecc handling is done on a 32-bit boundary and is completely software compatible with mpc55xx family devices containing an e200z6 core and 64-bit wide ecc. the sram module provides the following features: ? supports read/write accesses mapped to the sram from any master ? up to 20 kb general purpose sram ? supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory ? typical sram access time: no wait-state for reads and 32 -bit writes; 1 wait-state for 8- and 16-bit writes if back-to-back with a read to same memory block 1.5.6 interrupt controller (intc) the interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time system s. the intc handles 128 selectable-priority interrupt sources. for high-priority interrupt requests, the ti me from the assertion of the interrupt re quest by the peripheral to the execution o f the interrupt service routine (isr) by the processor has been mini mized. the intc provi des a unique vector for each interrupt request source for quick determination of which isr has to be ex ecuted. it also provides a wide number of priorities so that
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 10 lower priority isrs do not dela y the execution of higher priority isrs. to allow the approp riate priorities for each source of interrupt request, the priority of each in terrupt request is software configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol (pcp) for coherent accesses. by providing a modifiable pr iority mask, the priority ca n be raised temporarily s o that all tasks which share the same resource can not preempt each other. the intc provides the following features: ? unique 9-bit vector for each separate interrupt source ? 8 software triggerable interrupt sources ? 16 priority levels with fixed ha rdware arbitratio n within priority levels for each interrupt source ? ability to modify the isr or task priority: modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. ? 1 external high priority interrupt (nmi) directly accessing the main core and i/o proces sor (iop) critical interrupt mechanism 1.5.7 system status and co nfiguration module (sscm) the system status an d configuration module (sscm) provides central device functionality. the sscm includes these features: ? system configuration and status ? memory sizes/status ? device mode and security status ? determine boot vector ? search code flash for bootable sector ? dma status ? debug status port enable and selection ? bus and peripheral abort enable/disable 1.5.8 system clocks and clock generation the following list summarizes the system clock and clock generation on the mpc5602p: ? lock detect circuitry continuously monitors lock status ? loss of clock (loc) detection for pll outputs ? programmable output clock divider ( ? 1, ? 2, ? 4, ? 8) ? flexpwm module and etimer module running at the same frequency as the e200z0h core ? internal 16 mhz rc oscillator for rapid start-up and safe mode: supports frequency trimming by user application 1.5.9 frequency-modulated ph ase-locked loop (fmpll) the fmpll allows the user to generate hi gh speed system clocks from a 4?40 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor, output clock divider ratio are all software configurable. the fmpll has the follo wing major features: ? input clock frequency: 4?40 mhz ? maximum output frequency: 64 mhz ? voltage controlled oscillator (vco)?frequency 256?512 mhz ? reduced frequency divider (rfd) for reduced frequency operation without forcing the fmpll to relock
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 11 ? frequency-modulated pll ? modulation enabled/disabled through software ? triangle wave modulation ? programmable modulation depth (0.25% to 4% devia tion from center frequency) : programmable modulation frequency dependent on reference frequency ? self-clocked mode (scm) operation 1.5.10 main oscillator the main oscillator provides these features: ? input frequency range: 4?40 mhz ? crystal input mode or oscillator input mode ? pll reference 1.5.11 internal rc oscillator this device has an rc ladder phase-shift oscillator. the architecture us es constant current chargi ng of a capacitor. the voltag e at the capacitor is compared by th e stable bandgap reference voltage. the rc oscillator provides these features: ? nominal frequency 16 mhz ? 5% variation over voltage and temperature after process trim ? clock output of the rc oscillator serves as system clock source in case loss of lo ck or loss of clock is detected by the pll ? rc oscillator is used as the default system clock during startup 1.5.12 periodic interrupt timer (pit) the pit module implements these features: ? 4 general-purpose interrupt timers ? 32-bit counter resolution ? clocked by system clock frequency ? each channel usable as trigger for a dma request 1.5.13 system timer module (stm) the stm implements these features: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.5.14 software watchdog timer (swt) the swt has the following features: ? 32-bit time-out register to set the time-out period ? programmable selection of window mode or regular servicing
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 12 ? programmable selection of reset or interrupt on an initial time-out ? master access protection ? hard and soft configuration lock bits ? reset configuration inputs allow timer to be enabled out of reset 1.5.15 fault collection unit (fcu) the fcu provides an independent fault reporting mechanism even if the cpu is malfunctioning. the fcu module has the following features: ? fcu status register reporting the device status ? continuous monitoring of critical fault signals ? user selection of critical signals from different fault sources inside the device ? critical fault events trigger 2 external pins (user selected signal protocol) th at can be used externally to reset the device and/or other circuitry (for example, a safety relay) ? faults are latched into a register 1.5.16 system integrat ion unit ? lite (siul) the mpc5602p siul controls mcu pad configuration, external in terrupt, general purpose i/o (gpi o), and internal peripheral multiplexing. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the siul provides th e following features: ? centralized general purpose input output (gpio) control of up to 49 input/output pins and 16 analog input-only pads (package dependent) ? all gpio pins can be independently configur ed to support pull-up, pull-down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins, except adc channels, can be alternatively configured as both general purpose input or output pins ? adc channels support alternative configuration as general purpose inputs ? direct readback of the pin value is supported on all pins through the siul ? configurable digital input filter that can be applied to some general purpose input pins for noise elimination ? up to 4 internal functions can be multiplexed onto 1 pin 1.5.17 boot and censorship different booting modes are available in the mpc5602p: booting from internal flash memory and booting via a serial link. the default booting scheme uses the internal flash memory (an internal pull-down resistor is used to select this mode). optionally, the user can boot via flexcan or linflex (using the boot assist module software). a censorship scheme is provided to protect the content of the fl ash memory and offer increased security for the entire device. a password mechanism is designed to grant the legitimate user access to the non-volatile memory. 1.5.17.1 boot assis t module (bam) the bam is a block of read-only memory that is programmed once and is identical for all mpc560xp devices that are based on the e200z0h core. the bam program is executed every time th e device is powered on if the alternate boot mode has been selected by the user.
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 13 the bam provides the following features: ? serial bootloading via flexcan or linflex ? ability to accept a password via the used serial communication ch annel to grant the legitimate user access to the non-volatile memory 1.5.18 error correction status module (ecsm) the ecsm provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a so ftware watchdog timer, wakeup control for exiting sleep modes, and information on platform me mory errors reported by error-correcting code s and/or generic access error information for certain processor cores. the error correction status module supports a number of miscellaneous control functio ns for the platform. the ecsm includes these features: ? registers for capturing information on platform memory errors if error-correcting codes (ecc) are implemented ? for test purposes, optional registers to specify the ge neration of double-bit memory errors are enabled on the mpc5602p. the sources of the ecc errors are: ? flash memory ?sram 1.5.19 peripheral bridge (pbridge) the pbridge implements the following features: ? duplicated periphery ? master access privilege level per peripheral (per master: read access enable; write access enable) ? write buffering for peripherals ? checker applied on pbridge output toward periphery ? byte endianess swap capability 1.5.20 controller area network (flexcan) the mpc5602p mcu contains one controller area network (flexc an) module. this module is a communication controller implementing the can prot ocol according to bosch specificat ion version 2.0b. the can protoc ol was designed to be used primarily as a vehicle serial data bus, meet ing the specific requirements of this fiel d: real-time processing, reliable operati on in the emi environment of a vehicle, cost -effectiveness and required bandwidth. th e flexcan module contains 32 message buffers. the flexcan module provides the following features: ? full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? up to 8-bytes data length ? programmable bit rate up to 1 mbit/s ? 32 message buffers of up to 8-bytes data length ? each message buffer configurable as rx or tx , all supporting standard and extended messages ? programmable loop-back mode supporting self-test operation ? 3 programmable mask registers
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 14 ? programmable transmit-first scheme: lo west id or lowest buffer number ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? independent of the transmission medium (an external transceiver is assumed) ? high immunity to emi ? short latency time due to an arbitr ation scheme for high-priority messages ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter 1.5.21 safety port (flexcan) the mpc5602p mcu has a second can controller synthesized to r un at high bit rates to be used as a safety port. the can module of the safety port provides the following features: ? identical to the flexcan module ? bit rate up to 8 mbit/s at 64 mhz cpu clock using direct connection between can modules (no physical transceiver required) ? 32 message buffers of up to 8-bytes data length ? can be used as a second independent can module 1.5.22 serial communication interface module (linflex) the linflex (local interconnect network flexible) on the mpc5602p features the following: ? supports lin master mode (both instances), li n slave mode (only one instance) and uart mode ? lin state machine compliant to lin1.3, 2.0 and 2.1 specifications ? handles lin frame transmission an d reception without cpu intervention ? lin features ? autonomous lin frame handling ? message buffer to store identifier and up to 8 data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors (sync field, delimiter, id parity , bit framing, checksum, and time-out) ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features: loop back; self test; lin bus stuck dominant detection ? interrupt-driven operation with 16 interrupt sources
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 15 ? lin slave mode features: ? autonomous lin header handling ? autonomous lin response handling ? optional discarding of irrelevant lin responses using id filter ? uart mode: ? full-duplex operation ? standard non return-to-ze ro (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt-driven operation with four interrupt sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate m odulus counter and 16-bit fractional ? 2 receiver wake-up methods 1.5.23 deserial serial pe ripheral interface (dspi) the deserial serial peripheral interface (d spi) module provides a sy nchronous serial interface fo r communication between the mpc5602p mcu and external devices. the dspi modules prov ide these features: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits ? up to 8 chip select lines available: ? 8 on dspi_0 ? 4 each on dspi_1 and dspi_2 ? 8 clock and transfer attributes registers ? chip select strobe available as alternate function on one of the chip select pins for deglitching ? fifos for buffering up to 4 transfer s on the transmit and receive side ? queueing operation possible through use of the i/o processor or edma ? general purpose i/o functionality on pins when not used for spi 1.5.24 pulse width modulator (flexpwm) the pulse width modulator module (pwm) contains four pwm submodules each of which is set up to control a single half-bridge power stage. there are also three fault channels. this pwm is capable of controlling most motor types: ac induction motors (acim), permanent magnet ac motors (pmac), both brushless (bldc) and brush dc motors (bdc), switched (srm) and variable reluctance motors (vrm), and stepper motors. the flexpwm block implements the following features: ? 16-bit resolution for center, edge-aligned, and asymmetrical pwms
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 16 ? clock frequency same as that used for e200z0h core ? pwm outputs can operate as complementary pairs or independent channels ? can accept signed numbers for pwm generation ? independent control of both edges of each pwm output ? synchronization to external hardware or other pwm supported ? double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability ? multiple adc trigger events can be generated per pwm cycle via hardware ? write protection for critical registers ? fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? independent top and bottom deadtime insertion ? each complementary pair can operate with its own pwm frequency and deadtime values ? individual software-control for each pwm output ? all outputs can be progra mmed to change simultaneous ly via a ?force out? event ? pwmx pin can optionally output a th ird pwm signal from each submodule ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation can be used for input capture functions ? enhanced dual-edge capture functionality ? edma support with automatic reload ? 2 fault inputs ? capture capability for pwma, pwmb, and pwmx channels not supported 1.5.25 etimer the mpc5602p includes one etimer module which provides si x 16-bit general purpose up/down timer/counter units with the following features: ? clock frequency same as that used for the e200z0h core ? individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) ? maximum count rate ? external event counting: max. count rate = peripheral clock/2 ? internal clock counting: max. count rate = peripheral clock ? counters are: ? cascadable ? preloadable ? programmable count modulo ? quadrature decode capabilities
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 17 ? counters can share available input pins ? count once or repeatedly ? pins available as gpio when timer functionality not in use 1.5.26 analog-to-digital converter (adc) module the adc module provides the following features: analog part: ? 1 on-chip analog-to-digital converter ? 10-bit ad resolution ? 1 sample and hold unit ? conversion time, including sampling time, less than 1 s (at full precision) ? typical sampling time is 150 ns minimum (at full precision) ? dnl/inl 1 lsb ?tue <1.5lsb ? single-ended input signal up to 3.3 v/5.0 v ? 3.3 v/5.0 v input reference voltage ? adc and its reference can be supplied with a voltage independent from v ddio ? adc supply can be equal or higher than v ddio ? adc supply and adc reference are not independent fr om each other (both internally bonded to same pad) ? sample times of 2 (default), 8, 64 or 128 adc clock cycles digital part: ? 16 input channels ? 4 analog watchdogs comparing adc results against predefined levels (low, high, range) before results are stored in the appropriate adc result location ? 2 modes of operation: motor control mode or regular mode ? regular mode features ? register based interface with the cpu: control register, status register and 1 result register per channel ? adc state machine managing 3 request flows: regular command, hardware inject ed command and software injected command ? selectable priority between softwa re and hardware injected commands ? dma compatible interface ? ctu-controlled mode features ? triggered mode only ? 4 independent result queues (116 entries, 28 entries, 14 entries) ? result alignment circuitry (left justified and right justified) ? 32-bit read mode allows to have channel id on one of the 16-bit part ? dma compatible interfaces 1.5.27 cross triggering unit (ctu) the cross triggering unit allows automatic generation of adc conversion requests on user selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration. it implements the following features: ? double buffered trigger generation unit with up to 8 independent triggers generated from external triggers
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 18 ? trigger generation unit configurable in sequential mode or in triggered mode ? each trigger can be appropriately delayed to co mpensate the delay of external low pass filter ? double buffered global trigger unit allowing etimer synchronization and/or adc command generation ? double buffered adc command list pointers to minimize adc-trigger unit update ? double buffered adc conversion command list with up to 24 adc commands ? each trigger capable of generating consecutive commands ? adc conversion command allows to co ntrol adc channel, single or synchronous sampling, independent result queue selection 1.5.28 nexus development interface (ndi) the ndi (nexus development interface) bl ock provides real-time deve lopment support cap abilities for the mpc5602p power architecture based mcu in compliance with the ieee-isto 5001- 2003 standard. this developmen t support is supplied for mcus without requiring external address and data pins for inte rnal visibility. the ndi block is an integration of several individual nexus blocks that are selected to provide the develo pment support interface for this device. the ndi block interface s to the host processor and internal busses to provide development sup port as per the ieee-isto 5001-2003 class 2+ standard. the development support provided includes access to the mcu?s internal memo ry map and access to the processor?s internal registers during run time. the ndi provides the following features: ? configured via the ieee 1149.1 ? all nexus port pins operate at v ddio (no dedicated power supply) ? nexus 2+ features supported ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory mapped resources through jtag pins ? overrun control, which selects whether to stall before nexus overruns or keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing ? auxiliary output port ? 4 mdo (message data out) pins ? mcko (message clock out) pin ?2 mseo (message start/end out) pins ?evto (event out) pin ? auxiliary input port ?evti (event in) pin 1.5.29 cyclic redu ndancy check (crc) the crc computing unit is dedicated to the computatio n of crc off-loading the cp u. the crc module features: ? support for crc-16-ccitt ( x 25 protocol): ? x 16 + x 12 + x 5 + 1 ? support for crc-32 (e thernet protocol): ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? zero wait states for each write/read operations to th e crc_cfg and crc_inp register s at the maximum frequency
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 19 1.5.30 ieee 1149.1 jtag controller the jtag controller (jtagc) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. the jtag controller provides the following features: ? ieee test access port (tap) interface 4 pins (tdi, tms, tck, tdo) ? selectable modes of operation include jt agc/debug or normal system operation. ? 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ?bypass ? idcode ?extest ?sample ? sample/preload ? 5-bit instruction register that supports the additional following public instructions: ? access_aux_tap_npc ? access_aux_tap_once ? 3 test data registers: ? bypass register ? boundary scan register (size parameterized to support a variety of boundary scan chain lengths) ? device identification register ? tap controller state machine that cont rols the operation of the data register s, instruction regist er and associated circuitry 1.5.31 on-chip voltage regulator (vreg) the on-chip voltage regulator module provides the following features: ? uses external npn (negative- positive-negative) transistor ? regulates external 3.3 v/5.0 v down to 1.2 v for the core logic ? low voltage detection on the internal 1.2 v and i/o voltage 3.3 v 2 package pinouts and signal descriptions 2.1 package pinouts the lqfp pinouts are shown in the following figures. for pin signal descriptions, please refer to table 5 .
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 20 figure 2. 64-pin lqfp pinout(top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nmi a[6] a[7] a[8] a[5] vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] vss_lv_cor0 vdd_lv_cor0 a[4] vpp_test d[14]] d[12] d[13 vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi c[12] c[11] d[7] e[1] c[1] b[7] c[2] b[8] e[2] b[9] b[10] b[11] b[12] vdd_hv_adc0 vss_hv_adc0 e[3]/b[13] bctrl vdd_hv_reg a[15] a[14] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] vss_hv_io3 vdd_hv_io3 a[12] a[11] a[10] b[2] b[1] b[0] 64 lqfp
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 21 figure 3. 100-pin lqfp pinout (top view) 2.2 pin description the following sections provide signal descriptions and relate d information about the functionality and configuration of the mpc5602p devices. 2.2.1 power supply and reference voltage pins table 3 lists the power supply and reference voltage for the mpc5602p devices. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nmi a[6] d[1] a[7] c[4] a[8] c[5] a[5] c[7] c[3] n.c. n.c. vdd_hv_io1 vss_hv_io1 d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_cor0 vdd_lv_cor0 a[4] vpp_test d[14] c[14] c[13] d[12] n.c. n.c. d[13] vss_lv_cor1 vdd_lv_cor1 a[3] vdd_hv_io2 vss_hv_io2 tdo tck tms tdi a[2] c[12] c[11] d[11] d[10] a[1] a[0] d[7] e[1] c[1] b[7] c[2] b[8] e[2] n.c. n.c. b[9] b[10] b[11] b[12] vdd_hv_adc0 vss_hv_adc0 e[7]/d[15] e[3]/b[13] e[5]/b[15] e[4]/b[14] e[6]/c[0] n.c. bctrl n.c. n.c. vdd_hv_reg a[15] a[14] c[6] d[2] b[6] a[13] a[9] vss_lv_cor2 vdd_lv_cor2 c[8] d[4] d[3] vss_hv_io3 vdd_hv_io3 d[0] c[15] c[9] a[12] a[11] a[10] b[3] b[2] c[10] b[1] b[0] 100 lqfp
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 22 table 3. supply pins supply pin symbol description 64-pin 100-pin vreg control and power supply pins. pins available on 64-pin and 100-pin packages bctrl voltage regulator external npn ballast base control pin 31 47 v dd_hv_reg (3.3 v or 5.0 v) voltage regulator supply voltage 32 50 adc_0 reference and supply voltage. pins available on 64-pin and 100-pin packages v dd_hv_adc0 1 1 analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a double-bonding connection on v dd_hv_adcx /v ss_hv_adcx pins. adc_0 supply and high reference voltage 28 39 v ss_hv_adc0 adc_0 ground and low reference voltage 29 40 power supply pins (3.3 v or 5.0 v). pins available on 64-pin and 100-pin packages v dd_hv_io1 input/output supply voltage 6 13 v ss_hv_io1 input/output ground 7 14 v dd_hv_io2 input/output supply voltage and data flash memory supply voltage 40 63 v ss_hv_io2 input/output ground and flash memory hv ground 39 62 v dd_hv_io3 input/output supply voltage and code flash memory supply voltage 55 87 v ss_hv_io3 input/output ground and code fl ash memory hv ground 56 88 v dd_hv_osc crystal oscillator amplifier supply voltage 9 16 v ss_hv_osc crystal oscillator amplifier ground 10 17 power supply pins (1.2 v). pins available on 64-pin and 100-pin packages v dd_lv_cor0 1.2 v supply pins for core logic and pll. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 16 25 v ss_lv_cor0 1.2 v supply pins for core logic and pll. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 15 24 v dd_lv_cor1 1.2 v supply pins for core logic and data flash. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 42 65 v ss_lv_cor1 1.2 v supply pins for core logic and data flash. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 43 66 v dd_lv_cor2 1.2 v supply pins for core logic and code flash. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 58 92 v ss_lv_cor2 1.2 v supply pins for core logic and code flash. decoupling capacitor must be connected betwee.n these pins and the nearest v dd_lv_cor pin. 59 93
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 23 2.2.2 system pins table 4 and table 5 contain information on pin functions for the mpc5602p devices. the pins listed in table 4 are single-function pins. the pins shown in table 5 are multi-function pins, programmable via their respective pad configuration register (pcr) values. 2.2.3 pin multiplexing table 5 defines the pin list and muxing for the mpc5602p devices. each row of table 5 shows all the possible ways of conf iguring each pin, via alternate func tions. the default function assigned to each pin after reset is the alt0 function. mpc5602p devices provide three main i/o pad types, depending on the associated functions: ? slow pads are the most common, providing a compromise between transition tim e and low electromagnetic emission. ? medium pads provide fast enough transition for serial communication channels w ith controlled current to reduce electromagnetic emission. ? fast pads provide maximum speed. they are used for improved nexus debugging capability. medium and fast pads can use slow config uration to reduce electromagnetic emission, at the cost of reducing ac performance. for more information, see ?pad ac sp ecifications? in the device data sheet. table 4. system pins symbol description direction pad speed 1 1 src values refer to the value assigned to the slew ra te control bits of the pad configuration register. pin src = 0 src = 1 64-pin 100-pin dedicated pins nmi non-maskable interrupt input only slow ? 1 1 xtal analog output of the oscillator amplifier circuit?needs to be grounded if oscillator is used in bypass mode ???1118 extal analog input of the oscillator amplifier circuit, when the oscillator is not in bypass mode analog input for the clock generator when the oscillator is in bypass mode ???1219 tdi jtag test data input input only slow ? 35 58 tms jtag state machine control input only slow ? 36 59 tck jtag clock input only slow ? 37 60 tdo jtag test data output output only slow fast 38 61 reset pin reset bidirectional reset with schmitt trigger characteristics and noise filter bidirectional medium ? 13 20 test pin vpp_test pin for testing purpose only. to be tied to ground in normal operating mode. ???4774
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 24 table 5. pin muxing port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin port a (16-bit) a[0] pcr[0] alt0 alt1 alt2 alt3 ? gpio[0] etc[0] sck f[0] eirq[0] siul etimer_0 dspi_2 fcu_0 siul i/o i/o i/o o i slow medium ? 51 a[1] pcr[1] alt0 alt1 alt2 alt3 ? gpio[1] etc[1] sout f[1] eirq[1] siul etimer_0 dspi_2 fcu_0 siul i/o i/o o o i slow medium ? 52 a[2] pcr[2] alt0 alt1 alt2 alt3 ? ? ? gpio[2] etc[2] ? a[3] sin abs[0] eirq[2] siul etimer_0 ? flexpwm_0 dspi_2 mc_rgm siul i/o i/o ? o i i i slow medium ? 57 a[3] pcr[3] alt0 alt1 alt2 alt3 ? ? gpio[3] etc[3] cs0 b[3] abs[1] eirq[3] siul etimer_0 dspi_2 flexpwm_0 mc_rgm siul i/o i/o i/o o i i slow medium 41 64 a[4] pcr[4] alt0 alt1 alt2 alt3 ? ? gpio[4] ? cs1 etc[4] fab eirq[4] siul ? dspi_2 etimer_0 mc_rgm siul i/o ? o i/o i i slow medium 48 75 a[5] pcr[5] alt0 alt1 alt2 alt3 ? gpio[5] cs0 ? cs7 eirq[5] siul dspi_1 ? dspi_0 siul i/o i/o ? o i slow medium 5 8 a[6] pcr[6] alt0 alt1 alt2 alt3 ? gpio[6] sck ? ? eirq[6] siul dspi_1 ? ? siul i/o i/o ? ? i slow medium 2 2 a[7] pcr[7] alt0 alt1 alt2 alt3 ? gpio[7] sout ? ? eirq[7] siul dspi_1 ? ? siul i/o o ? ? i slow medium 3 4
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 25 a[8] pcr[8] alt0 alt1 alt2 alt3 ? ? gpio[8] ? ? ? sin eirq[8] siul ? ? ? dspi_1 siul i/o ? ? ? i i slow medium 4 6 a[9] pcr[9] alt0 alt1 alt2 alt3 ? gpio[9] cs1 ? b[3] fault[0] siul dspi_2 ? flexpwm_0 flexpwm_0 i/o o ? o i slow medium 60 94 a[10] pcr[10] alt0 alt1 alt2 alt3 ? gpio[10] cs0 b[0] x[2] eirq[9] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o i/o o o i slow medium 52 81 a[11] pcr[11] alt0 alt1 alt2 alt3 ? gpio[11] sck a[0] a[2] eirq[10] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o i/o o o i slow medium 53 82 a[12] pcr[12] alt0 alt1 alt2 alt3 ? gpio[12] sout a[2] b[2] eirq[11] siul dspi_2 flexpwm_0 flexpwm_0 siul i/o o o o i slow medium 54 83 a[13] pcr[13] alt0 alt1 alt2 alt3 ? ? ? gpio[13] ? b[2] ? sin fault[0] eirq[12] siul ? flexpwm_0 ? dspi_2 flexpwm_0 siul i/o ? o ? i i i slow medium 61 95 a[14] pcr[14] alt0 alt1 alt2 alt3 ? gpio[14] txd ? ? eirq[13] siul safety port_0 ? ? siul i/o o ? ? i slow medium 63 99 a[15] pcr[15] alt0 alt1 alt2 alt3 ? ? gpio[15] ? ? ? rxd eirq[14] siul ? ? ? safety port_0 siul i/o ? ? ? i i slow medium 64 100 table 5. pin muxing (continued) port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 26 port b (16-bit) b[0] pcr[16] alt0 alt1 alt2 alt3 ? gpio[16] txd ? debug[0] eirq[15] siul flexcan_0 ? sscm siul i/o o ? ? i slow medium 49 76 b[1] pcr[17] alt0 alt1 alt2 alt3 ? ? gpio[17] ? ? debug[1] rxd eirq[16] siul ? ? sscm flexcan_0 siul i/o ? ? ? i i slow medium 50 77 b[2] pcr[18] alt0 alt1 alt2 alt3 ? gpio[18] txd ? debug[2] eirq[17] siul lin_0 ? sscm siul i/o o ? ? i slow medium 51 79 b[3] pcr[19] alt0 alt1 alt2 alt3 ? gpio[19] ? ? debug[3] rxd siul ? ? sscm lin_0 i/o ? ? ? i slow medium ? 80 b[6] pcr[22] alt0 alt1 alt2 alt3 ? gpio[22] clkout cs2 ? eirq[18] siul control dspi_2 ? siul i/o o o ? i slow medium 62 96 b[7] pcr[23] alt0 alt1 alt2 alt3 ? ? gpio[23] ? ? ? an[0] rxd siul ? ? ? adc_0 lin_0 input only ? ? 20 29 b[8] pcr[24] alt0 alt1 alt2 alt3 ? ? gpio[24] ? ? ? an[1] etc[5] siul ? ? ? adc_0 etimer_0 input only ? ? 22 31 b[9] pcr[25] alt0 alt1 alt2 alt3 ? gpio[25] ? ? ? an[11] siul ? ? ? adc_0 input only ? ? 24 35 table 5. pin muxing (continued) port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 27 b[10] pcr[26] alt0 alt1 alt2 alt3 ? gpio[26] ? ? ? an[12] siul ? ? ? adc_0 input only ? ? 25 36 b[11] pcr[27] alt0 alt1 alt2 alt3 ? gpio[27] ? ? ? an[13] siul ? ? ? adc_0 input only ? ? 26 37 b[12] pcr[28] alt0 alt1 alt2 alt3 ? gpio[28] ? ? ? an[14] siul ? ? ? adc_0 input only ? ? 27 38 b[13] pcr[29] alt0 alt1 alt2 alt3 ? ? ? gpio[29] ? ? ? an[6] emu. an[0] rxd siul ? ? ? adc_0 emu. adc_1 6 lin_1 input only ? ? 30 42 b[14] pcr[30] alt0 alt1 alt2 alt3 ? ? ? ? gpio[30] ? ? ? an[7] emu. an[1] etc[4] eirq[19] siul ? ? ? adc_0 emu. adc_1 6 etimer_0 siul input only ? ? ? 44 b[15] pcr[31] alt0 alt1 alt2 alt3 ? ? ? gpio[31] ? ? ? an[8] emu. an[2] eirq[20] siul ? ? ? adc_0 emu. adc_1 6 siul input only ? ? ? 43 port c (16-bit) c[0] pcr[32] alt0 alt1 alt2 alt3 ? ? gpio[32] ? ? ? an[9] emu. an[3] siul ? ? ? adc_0 emu. adc_1 6 input only ? ? ? 45 table 5. pin muxing (continued) port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 28 c[1] pcr[33] alt0 alt1 alt2 alt3 ? gpio[33] ? ? ? an[2] siul ? ? ? adc_0 input only ? ? 19 28 c[2] pcr[34] alt0 alt1 alt2 alt3 ? gpio[34] ? ? ? an[3] siul ? ? ? adc_0 input only ? ? 21 30 c[3] pcr[35] alt0 alt1 alt2 alt3 ? gpio[35] cs1 ? txd eirq[21] siul dspi_0 ? lin_1 siul i/o o ? o i slow medium ? 10 c[4] pcr[36] alt0 alt1 alt2 alt3 ? gpio[36] cs0 x[1] debug[4] eirq[22] siul dspi_0 flexpwm_0 sscm siul i/o i/o o ? i slow medium ? 5 c[5] pcr[37] alt0 alt1 alt2 alt3 ? gpio[37] sck ? debug[5] eirq[23] siul dspi_0 ? sscm siul i/o i/o ? ? i slow medium ? 7 c[6] pcr[38] alt0 alt1 alt2 alt3 ? gpio[38] sout b[1] debug[6] eirq[24] siul dspi_0 flexpwm_0 sscm siul i/o o o ? i slow medium ? 98 c[7] pcr[39] alt0 alt1 alt2 alt3 ? gpio[39] ? a[1] debug[7] sin siul ? flexpwm_0 sscm dspi_0 i/o ? o ? i slow medium ? 9 c[8] pcr[40] alt0 alt1 alt2 alt3 gpio[40] cs1 ? cs6 siul dspi_1 ? dspi_0 i/o o ? o slow medium 57 91 c[9] pcr[41] alt0 alt1 alt2 alt3 gpio[41] cs3 ? x[3] siul dspi_2 ? flexpwm_0 i/o o ? o slow medium ? 84 table 5. pin muxing (continued) port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 29 c[10] pcr[42] alt0 alt1 alt2 alt3 ? gpio[42] cs2 ? a[3] fault[1] siul dspi_2 ? flexpwm_0 flexpwm_0 i/o o ? o i slow medium ? 78 c[11] pcr[43] alt0 alt1 alt2 alt3 gpio[43] etc[4] cs2 ? siul etimer_0 dspi_2 ? i/o i/o o ? slow medium 33 55 c[12] pcr[44] alt0 alt1 alt2 alt3 gpio[44] etc[5] cs3 ? siul etimer_0 dspi_2 ? i/o i/o o ? slow medium 34 56 c[13] pcr[45] alt0 alt1 alt2 alt3 ? ? gpio[45] ? ? ? ext_in ext_sync siul ? ? ? ctu_0 flexpwm_0 i/o ? ? ? i i slow medium ? 71 c[14] pcr[46] alt0 alt1 alt2 alt3 gpio[46] ? ext_tgr ? siul ? ctu_0 ? i/o ? o ? slow medium ? 72 c[15] pcr[47] alt0 alt1 alt2 alt3 ? ? gpio[47] ? ? a[1] ext_in ext_sync siul ? ? flexpwm_0 ctu_0 flexpwm_0 i/o ? ? o i i slow medium ? 85 port d (16-bit) d[0] pcr[48] alt0 alt1 alt2 alt3 gpio[48] ? ? b[1] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 86 d[1] pcr[49] alt0 alt1 alt2 alt3 gpio[49] ? ? ext_trg siul ? ? ctu_0 i/o ? ? o slow medium ? 3 d[2] pcr[50] alt0 alt1 alt2 alt3 gpio[50] ? ? x[3] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 97 d[3] pcr[51] alt0 alt1 alt2 alt3 gpio[51] ? ? a[3] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 89 table 5. pin muxing (continued) port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 30 d[4] pcr[52] alt0 alt1 alt2 alt3 gpio[52] ? ? b[3] siul ? ? flexpwm_0 i/o ? ? o slow medium ? 90 d[5] pcr[53] alt0 alt1 alt2 alt3 gpio[53] cs3 f[0] ? siul dspi_0 fcu_0 ? i/o o o ? slow medium ? 22 d[6] pcr[54] alt0 alt1 alt2 alt3 ? gpio[54] cs2 ? ? fault[1] siul dspi_0 ? ? flexpwm_0 i/o o ? ? i slow medium ? 23 d[7] pcr[55] alt0 alt1 alt2 alt3 gpio[55] cs3 f[1] cs4 siul dspi_1 fcu_0 dspi_0 i/o o o o slow medium 17 26 d[8] pcr[56] alt0 alt1 alt2 alt3 gpio[56] cs2 ? cs5 siul dspi_1 ? dspi_0 i/o o ? o slow medium 14 21 d[9] pcr[57] alt0 alt1 alt2 alt3 gpio[57] x[0] txd ? siul flexpwm_0 lin_1 ? i/o o o ? slow medium 8 15 d[10] pcr[58] alt0 alt1 alt2 alt3 gpio[58] a[0] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 53 d[11] pcr[59] alt0 alt1 alt2 alt3 gpio[59] b[0] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium ? 54 d[12] pcr[60] alt0 alt1 alt2 alt3 ? gpio[60] x[1] ? ? rxd siul flexpwm_0 ? ? lin_1 i/o o ? ? i slow medium 45 70 d[13] pcr[61] alt0 alt1 alt2 alt3 gpio[61] a[1] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium 44 67 d[14] pcr[62] alt0 alt1 alt2 alt3 gpio[62] b[1] ? ? siul flexpwm_0 ? ? i/o o ? ? slow medium 46 73 table 5. pin muxing (continued) port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 31 d[15] pcr[63] alt0 alt1 alt2 alt3 ? ? gpio[63] ? ? ? an[10] emu. an[4] siul ? ? ? adc_0 emu. adc_1 6 input only ? ? ? 41 port e (16-bit) e[0] pcr[64] alt0 alt1 alt2 alt3 ? gpio[64] ? ? ? an[15] siul ? ? ? adc_0 input only ? ? ? 46 e[1] pcr[65] alt0 alt1 alt2 alt3 ? gpio[65] ? ? ? an[4] siul ? ? ? adc_0 input only ? ? 18 27 e[2] pcr[66] alt0 alt1 alt2 alt3 ? gpio[66] ? ? ? an[5] siul ? ? ? adc_0 input only ? ? 23 32 e[3] pcr[67] alt0 alt1 alt2 alt3 ? gpio[67] ? ? ? an[6] siul ? ? ? adc_0 input only ? ? 30 42 e[4] pcr[68] alt0 alt1 alt2 alt3 ? gpio[68] ? ? ? an[7] siul ? ? ? adc_0 input only ? ? ? 44 e[5] pcr[69] alt0 alt1 alt2 alt3 ? gpio[69] ? ? ? an[8] siul ? ? ? adc_0 input only ? ? ? 43 e[6] pcr[70] alt0 alt1 alt2 alt3 ? gpio[70] ? ? ? an[9] siul ? ? ? adc_0 input only ? ? ? 45 e[7] pcr[71] alt0 alt1 alt2 alt3 ? gpio[71] ? ? ? an[10] siul ? ? ? adc_0 input only ? ? ? 41 table 5. pin muxing (continued) port pin pcr register alternate function 1,2 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 64-pin 100-pin
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 32 1 alt0 is the primary (default) fu nction for each port after reset. 2 alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siu module. pcr.pa = 00 ? alt0; pcr.pa = 01 ? alt1; pcr.pa = 10 ? alt2; pcr.pa = 11 ? alt3. this is intended to select the output functions; to use one of the input functions, the pcr.ibe bit mu st be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this re ason, the value corresponding to an input only function is reported as ???. 3 module included on the mcu. 4 multiple inputs are routed to all respective modules in ternally. the input of some modules must be configured by setting the values of the psmio.padsel x bitfields inside the siul module. 5 programmable via the src (slew rate control) bits in the respective pad configuration register. 6 adc0.an emulates adc1.an. this feature is used to provide software compatibility between mpc5602p and mpc5604p. refer to adc chapter of reference manual for more details.
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 33 3 electrical characteristics 3.1 introduction this section contains device electri cal characteristics as well as temp erature and power considerations. this microcontroller contains input protection against damage due to high static voltages. however, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this can be done by the internal pull-up or pull-down resistors, which are pr ovided by the device for most general purpose pins. the following tables provide the device char acteristics and its de mands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. caution all of the following parameter values can vary depending on the application and must be confirmed during silicon characteri zation or silicon reliability trial. 3.2 parameter classification the electrical parameters are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 6 are used and the parameters are tagged ac cordingly in the tabl es where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 absolute maximum ratings table 6. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size ac ross process variations. t those parameters are achieved by design characte rization on a small samp le size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 7. absolute maximum ratings 1 symbol parameter conditions value unit min max v ss sr device ground ? 0 0 v
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 34 v dd_hv_iox 2 sr 3.3 v/5.0 v input/output supply voltage (supply). code flash memory supply with v dd_hv_io3 and data flash memory with v dd_hv_io2 ??0.3 6.0v v ss_hv_iox sr 3.3 v/5.0 v input/output supply voltage (ground). code flash memory ground with v ss_hv_io3 and data flash memory with v ss_hv_io2 ??0.1 0.1v v dd_hv_osc sr 3.3 v/5.0 v crystal oscillator amplifier supply voltage (supply) ??0.3 6.0v relative to v dd_hv_iox ?0.3 v dd_hv_iox +0.3 v ss_hv_osc sr 3.3 v/5.0 v crystal oscillator amplifier supply voltage (ground) ??0.1 0.1v v dd_hv_adc0 sr 3.3 v/5.0 v adc_0 supply and high- reference voltage v dd_hv_reg < 2.7 v ?0.3 v dd_hv_reg +0.3 v v dd_hv_reg > 2.7 v ?0.3 6.0 v ss_hv_adc0 sr 3.3 v/5.0 v adc_0 ground and low- reference voltage ??0.1 0.1v v dd_hv_reg sr 3.3 v/5.0 v voltage-regulator supply voltage ??0.3 6.0v relative to v dd_hv_iox ?0.3 v dd_hv_iox +0.3 tv dd sr slope characteristics on all v dd during power up 3 ? ? 0.25 v/s v dd_lv_corx cc 1.2 v supply pins for core logic (supply) ??0.1 1.5v v ss_lv_corx sr 1.2 v supply pins for core logic (ground) ??0.1 0.1v v in sr voltage on any pin with respect to ground (v ss_hv_iox ) ??0.3 6.0v relative to v dd_hv_iox ?0.3 v dd_hv_iox +0.3 4 i injpad sr input current on any pin during overload condition ??10 10ma i injsum sr absolute sum of all input currents during overload condition ??50 50ma t stg sr storage temperature ? ?55 150 c t j sr junction temperature under bias ? ? 40 150 c table 7. absolute maximum ratings 1 (continued) symbol parameter conditions value unit min max
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 35 figure 4 shows the constraints of the different power supplies. figure 4. power supplies constraints (?0.3 v ? v dd_hv_iox ? 6.0 v) the mpc5602p supply architecture allows the adc supply to be managed independently from the standard v dd_hv supply. figure 5 shows the constraints of the adc power supply. 1 functional operating conditions are given in the dc electric al characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is no t guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 the difference between each couple of voltage supplies must be less than 300 mv, ? v dd_hv_ioy ?v dd_hv_iox ? <300mv. 3 guaranteed by device validation. 4 only when v dd_hv_iox < 5.2 v vdd_hv_xxx vdd_hv_iox ?0.3 v 6.0 v ?0.3 v 6.0 v
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 36 figure 5. independent adc supply (?0.3 v ? v dd_hv_reg ? 6.0 v) 3.4 recommended operating conditions table 8. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max 1 v ss sr device ground ? 0 0 v v dd_hv_iox 2 sr 5.0 v input/output supply voltage ?4.55.5v v ss_hv_iox sr input/output ground voltage ?00v v dd_hv_osc sr 5.0 v crystal oscillator amplifier supply voltage ?4.55.5v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 5.0 v crystal oscillator amplifier reference voltage ?00v v dd_hv_reg sr 5.0 v voltage regulator supply voltage ?4.55.5v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1 v dd_hv_adc0 sr 5.0 v adc_0 supply and high reference voltage ?4.55.5v relative to v dd_hv_reg v dd_hv_reg ?0.1 ? vdd_hv_adcx 6.0 v vdd_hv_reg ?0.3 v 2.7 v ?0.3 v 6.0 v
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 37 v ss_hv_adc0 sr adc_0 ground and low reference voltage ?00v v dd_lv_regcor 3,4 cc internal supply voltage ? ? ? v v ss_lv_regcor 3 sr internal reference voltage ? 0 0 v v dd_lv_corx 3,4 cc internal supply voltage ? ? ? v v ss_lv_corx 3 sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias ? ? 40 125 c 1 full functionality cannot be guaranteed when voltage drops belo w 4.5 v. in particular, adc electrical characteristics and i/os dc electrical specification may not be guaranteed. 2 the difference between each couple of voltage supplies must be less than 100 mv, ? v dd_hv_ioy ?v dd_hv_iox ? <100mv. 3 to be connected to emitter of external npn. low voltage supplies are not under user cont rol?they are produced by an on-chip voltage regulator?but for the device to function properly the low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 4 the low voltage supplies (v dd_lv_xxx ) are not all independent. ? v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash memory module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. ? v dd_lv_regcor and v dd_lv_recorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 9. recommended operating conditions (3.3 v) symbol parameter conditions value unit min max 1 v ss sr device ground ? 0 0 v v dd_hv_iox 2 sr 3.3 v input/output supply voltage ?3.03.6v v ss_hv_iox sr input/output ground voltage ?00v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ?3.03.6v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ?00v v dd_hv_reg sr 3.3 v voltage regulator supply voltage ?3.03.6v relative to v dd_hv_iox v dd_hv_iox ?0.1 v dd_hv_iox +0.1 v dd_hv_adc0 sr 3.3 v adc_0 supply and high reference voltage ?3.05.5v relative to v dd_hv_reg v dd_hv_reg ? 0.1 5.5 table 8. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max 1
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 38 v ss_hv_adc0 sr adc_0 ground and low reference voltage ?00v v dd_lv_regcor 3,4 cc internal supply voltage ? ? ? v v ss_lv_regcor 3 sr internal reference voltage ? 0 0 v v dd_lv_corx 3,4 cc internal supply voltage ? ? ? v v ss_lv_corx 3 sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias ? ? 40 125 c 1 full functionality cannot be guaranteed when voltage drops below 3.0 v. in particular, adc electrical characteristics and i/os dc electrical specific ation may not be guaranteed. 2 the difference between each couple of voltage supplies must be less than 100 mv, ? v dd_hv_ioy ?v dd_hv_iox ? <100mv. 3 to be connected to emitter of exte rnal npn. low voltage supplies are not under user control?they are produced by an on-chip voltage regulator?but for the device to function properly t he low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 4 the low voltage supplies (v dd_lv_xxx ) are not all independent. ? v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding connections with lines that provide the low voltage supply to the data flash memory module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. ? v dd_lv_regcor and v dd_lv_recorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 9. recommended operating conditions (3.3 v) (continued) symbol parameter conditions value unit min max 1
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 39 figure 6 shows the constraints of the different power supplies. figure 6. power supplies constraints (3.0 v ? v dd_hv_iox ? 5.5 v) the mpc5602p supply architecture allows the adc supply to be managed independently from the standard v dd_hv supply. figure 7 shows the constraints of the adc power supply. figure 7. independent adc supply (3.0 v ? v dd_hv_reg ? 5.5 v) vdd_hv_xxx vdd_hv_iox 3.0 v 5.5 v 3.0 v 5.5 v 3.3 v 3.3 v note : io ac and dc characteristics are guaranteed only in the range of 3.0?3.6 v when pad3v5v is low, and in the range of 4.5?5.5 v when pad3v5v is high. 5.5 v 3.0 v vdd_hv_reg 3.0 v 5.5 v vdd_hv_adcx
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 40 3.5 thermal characteristics 3.5.1 package thermal characteristics 3.5.2 general notes for specificatio ns at maximum ju nction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : t j = t a + (r ? ja * p d ) eqn. 1 where: t a = ambient temperatur e for the package (c) r ? ja = junction-to-ambient thermal resistance (c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two va lues in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for pack ages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. th e value obtained on the board with the intern al planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed in equation 2 as the sum of a junction -to-case thermal resistance and a case-to-ambient thermal resistance: r ? ja = r ? jc + r ? ca eqn. 2 table 10. lqfp thermal characteristics symbol parameter conditions typical value unit 100-pin 64-pin r ? ja thermal resistance junction-to-ambient, natural convection 1 1 junction-to-ambient thermal resistance determined per jedec jesd51-7. thermal test board me ets jedec specification for this package. single layer board?1s 63 57 c/w four layer board?2s2p 51 41 c/w r ? jb thermal resistance junction-to-board 2 2 junction-to-board thermal resistance determined per jedec j esd51-8. thermal test board meets jedec specification for the specified package. when greek le tters are not available, the symbols are typed as rthjb or theta-jb. four layer board?2s2p 33 22 c/w r ? jctop thermal resistance junction-to-case (top) 3 3 junction-to-case at the top of the packa ge determined using mil-std 883 method 1012. 1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. single layer board?1s 15 13 c/w ? jb junction-to-board, natural convection 4 4 thermal characterization parameter indicating the temperature difference between the board and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization para meter is written as psi-jb. operating conditions 33 22 c/w ? jc junction-to-case, natural convection 5 5 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal ch aracterization parameter is written as psi-jc. operating conditions 1 1 c/w
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 41 where: r ? ja = junction-to-ambient thermal resistance (c/w) r ? jc = junction-to-case thermal resistance (c/w) r ? ca = case-to-ambient thermal resistance (c/w) r ? jc is device related and cannot be influenced by the user. the user controls the therma l environment to change the case-to-ambient thermal resistance, r ? ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, th e mounting arrangement on printe d circuit board, or change th e thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in th e application when heat sink s are not used, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using equation 3 : t j = t t + ( ? jt x p d ) eqn. 3 where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of e poxy is placed over the thermocoup le junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. references: ? semiconductor equipment and materials international 3081 zanker road san jose, ca 95134u.s.a. (408) 943-6900 ? mil-spec and eia/jesd (jedec) specifications are av ailable from global engineering documents at (800) 854-7179 or (303) 397-7956. ? jedec specifications are available on the web at http://www.jedec.org. ? c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module , proceedings of semitherm, san diego, 1998, pp. 47?54. ? g. kromann, s. shidore, and s. addison, thermal modeling of a pbga for air-cooled applications , electronic packaging and production, pp. 53?58, march 1998. ? b. joiner and v. adams, measurement and simulation of junction to board thermal resistance and its application in thermal modeling , proceedings of semitherm, san diego, 1999, pp. 212?220.
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 42 3.6 electromagnetic interference (emi) characteristics 3.7 electrostatic discharge (esd) characteristics 3.8 power management electrical characteristics 3.8.1 voltage regulator electrical characteristics the internal voltage regulator requires an external npn ( bcp68, bcx68 or bc817) ballast to be connected as shown in figure 8 . capacitances should be placed on the board as near as possible to the asso ciated pins. care should also be taken to limit the serial inductance of the board to less than 5 nh. table 11. emi testing specifications symbol parameter conditions clocks frequency level (typ) unit v eme radiated emissions v dd =5.0v; t a =25c other device configuration, test conditions and em testing per standard iec61967-2 f osc =8mhz f cpu =64mhz no pll frequency modulation 150 khz?150 mhz 11 dbv 150?1000 mhz 13 iec level m ? f osc =8mhz f cpu =64mhz 4% pll frequency modulation 150 khz?150 mhz 8 dbv 150?1000 mhz 12 iec level n ? v dd =3.3v; t a =25c other device configuration, test conditions and em testing per standard iec61967-2 f osc =8mhz f cpu =64mhz no pll frequency modulation 150 khz?150 mhz 9 dbv 150?1000 mhz 12 iec level m ? f osc =8mhz f cpu =64mhz 4% pll frequency modulation 150 khz?150 mhz 7 dbv 150?1000 mhz 12 iec level n ? table 12. esd ratings 1,2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperat ure followed by hot temperature, unl ess specified otherwise in the device specification. symbol parameter conditions value unit v esd(hbm) sr electrostatic discharge (human body model) ? 2000 v v esd(cdm) sr electrostatic discharge (charged device model) ? 750 (corners) v 500 (other)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 43 note the voltage regulator output cannot be used to drive external circuits. output pins are to be used only for decoupling capacitance. v dd_lv_cor must be generated using internal regulator and external npn transistor. it is not possible to provide v dd_lv_cor through external regulator. for the mpc5602p microcontroller, 10 f should be placed between each of the three v dd_lv_corx /v ss_lv_corx supply pairs and also between the v dd_lv_regcor /v ss_lv_regcor pair. additionally, 40 f sh ould be placed between the v dd_hv_reg /v ss_hv_reg pins. v dd = 3.0 v to 3.6 v / 4.5 v to 5.5 v, t a = ?40 to 125 c, unless otherwise specified. figure 8. voltage regulator configuration table 13. voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max v dd_lv_regcor cc p output voltage under maximum load run supply current configuration post-trimming 1.15 ? 1.32 v c dec1 sr ? external decoupling/stability ceramic capacitor bipolar bcp68 or bcx68 or bc817su three capacitances of 10 f 19.5 30 ? f bipolar bc817 one capacitance of 22 f 14.3 22 ? f r reg sr ? resulting esr of either one or all three c dec1 absolute maximum value between 100 khz and 10 mhz ??45m ? bctrl vdd_lv_cor c dec3 c dec2 c dec1 vdd_hv_reg bcp68, bcx68, bc817 mpc5602p
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 44 3.8.2 voltage monitor ele ctrical characteristics the device implements a power on reset module to ensure correct power-up initialization, as well as three low voltage detectors to monitor the v dd and the v dd_lv voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range ? lvdlvcor monitors low voltage digital power domain 3.9 power up/down sequencing to prevent an overstress even t or a malfunction within and outside the device, the mpc5602p implements the following sequence to ensure each module is started only wh en all conditions for switc hing it on are available: ? a power_on module working on voltage regulator supply cont rols the correct start-up of the regulator. this is a key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5 v. associated power_on (or por) signal is active low. c dec2 sr ? external decoupling/stability ceramic capacitor four capacitances of 440 nf each 1200 1760 ? nf c dec3 sr ? external decoupling/stability ceramic capacitor on vdd_hv_reg two capacitances of 10 f each 2 10 ? ? f table 14. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 c to t a max , unless otherwise specified value unit min max v porh t power-on reset th reshold ? 1.5 2.7 v v porup p supply for functional por module t a = 25 c 1.0 ? v v reglvdmok_h p regulator low voltage detector high threshold ? ? 2.95 v v reglvdmok_l p regulator low voltage detector low threshold ? 2.6 ? v v fllvdmok_h p flash low voltage detector high threshold ? ? 2.95 v v fllvdmok_l p flash low voltage detector low threshold ? 2.6 ? v v iolvdmok_h p i/o low voltage detector high threshold ? ? 2.95 v v iolvdmok_l p i/o low voltage detector low threshold ? 2.6 ? v v iolvdm5ok_h p i/o 5 v low voltage detector high threshold ? ? 4.4 v v iolvdm5ok_l p i/o 5 v low voltage detector low threshold ? 3.8 ? v v mlvddok_h p digital supply low voltage detector high ? ? 1.145 v v mlvddok_l p digital supply low voltage detector low ? 1.08 ? v table 13. voltage regulator electrical characteristics (continued) symbol c parameter conditions value unit min typ max
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 45 ? several low voltage detectors, working on voltage regulator su pply monitor the voltage of the critical modules (voltage regulator, i/os, flash memory and low voltage domain). lvds are gated low when power_on is active. ? a power_ok signal is generated when all critical supplies monitored by the lv d are available. th is signal is active high and released to all modules including i/os, flash memory and 16 mhz rc oscillator needed during power-up phase and reset phase. when power_ok is low th e associated modules are set into a safe state. figure 9. power-up typical sequence vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 0v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 p1 0v 1.2v internal reset generation module fsm ~1us v por_up v porh v lvdhv3h v mlvdok_h
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 46 figure 10. power-down typical sequence figure 11. brown-out typical sequence vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l v porh 0v vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l 0v v lvdhv3h p1 ~1us
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 47 3.10 dc electrical characteristics 3.10.1 nvusro register portions of the device configuration, such as high voltage supp ly, oscillator margin, and watch dog enable/disable after reset a re controlled via bit values in the non-vol atile user options (nvusro) register. for a detailed description of the nvusro regist er, please refer to the device reference manual. 3.10.1.1 nvusro[pad3v 5v] field description the dc electrical characteristics are dependent on the pad3v5v bit value. table 15 shows how nvusro[pad3v5v] controls the device configuration. 3.10.1.2 nvusro[oscillator_ margin] field description the fast external crystal oscillator consumption is dependent on the oscillator_margin bit value. table 16 shows how nvusro[oscillator_margin] cont rols the device configuration. 3.10.2 dc electrical characteristics (5 v) table 17 gives the dc electrical char acteristics at 5 v (4.5 v < v dd_hv_iox < 5.5 v, nvusro[pad3v5v] = 0). table 15. pad3v5v field description value 1 1 default manufacturing value before fl ash initialization is ?1? (3.3 v). description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 16. oscillator_margin field description value 1 1 default manufacturing value befo re flash initialization is ?1?. description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) table 17. dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value unit min max v il d low level input voltage ? ? 0.4 1 ?v p??0.35v dd_hv_iox v v ih p high level input voltage ? 0.65 v dd_hv_iox ?v d??v dd_hv_iox +0.4 1 v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 48 v oh_s p slow, high level output voltage i oh = ? 3ma 0.8v dd_hv_iox ?v v ol_m p medium, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_m p medium, high level output voltage i oh = ? 3ma 0.8v dd_hv_iox ?v v ol_f p fast, low level output voltage i ol =14ma ? 0.1v dd_hv_iox v v oh_f p fast, high level output voltage i oh = ? 14 ma 0.8 v dd_hv_iox ?v i pu p equivalent pull-up current v in =v il ? 130 ? a v in =v ih ? ? 10 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ?130 i il p input leakage current (all bidirectional ports) t a = ? 40 to 125 c ? 11a i il p input leakage current (all adc input-only ports) t a = ? 40 to 125 c ? 0.5 0.5 a c in d input capacitance ? ? 10 pf 1 ?sr? parameter values must not exceed the absolute maximum ratings shown in ta b l e 7 . table 18. supply current (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value 1 1 all values to be confirmed after characterization/data collection. unit typ max i dd_lv_corx t supply current run?maximum mode 2 2 maximum mode: flexpwm, adc, ctu, ds pi, linflex, flexcan, 15 output pins, pll_0 enabled, 125 c ambient. i/o supply current excluded. v dd_lv_corx externally forced at 1.3 v 40 mhz 44 55 ma p 64 mhz 52 65 t run?typical mode 3 3 typical mode configurations: dspi, li nflex, flexcan, 15 output pins, pll_ 0, 105 c ambient. i/o supply current excluded. 40 mhz 38 46 64 mhz 45 54 p halt mode 4 ?1.510 stop mode 5 ?110 i dd_flash t flash during read v dd_hv_fl at 5.0 v ? 8 10 flash during erase operation on 1 flash module v dd_hv_fl at 5.0 v ? 15 19 i dd_adc tadc v dd_hv_adc0 at 5.0 v f adc =16mhz adc_0 3 4 i dd_osc t oscillator v dd_hv_osc at 5.0 v 8 mhz 2.6 3.2 table 17. dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) (continued) symbol c parameter conditions value unit min max
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 49 4 halt mode configurations: code fetched from sram, co de flash memory and data flash memory in low power mode, osc/pll_0 are off, core clock frozen, all peripherals disabled. 5 stop ?p? mode device under test (dut) configuration: code fetched from sram, code flash memory and data flash memory off, osc/pll_0 are off, core clock frozen, all peripherals disabled.
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 50 3.10.3 dc electrical characteristics (3.3 v) table 19 gives the dc electrical charact eristics at 3.3 v (3.0 v < v dd_hv_iox < 3.6 v, nvusro[pad3v5v] = 1); see figure 12 . table 19. dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) 1 1 these specifications are design targets and subject to change per device characterization. symbol c parameter conditions value unit min max v il d low level input voltage ? ? 0.4 2 2 ?sr? parameter values must not exceed the absolute maximum ratings shown in ta b l e 7 . ?v p??0.35v dd_hv_iox v v ih p high level input voltage ? 0.65 v dd_hv_iox ?v d??v dd_hv_iox +0.4 2 v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol =1.5ma ? 0.5 v v oh_s p slow, high level output voltage i oh = ? 1.5 ma v dd_hv_iox ? 0.8 ? v v ol_m p medium, low level output voltage i ol =2ma ? 0.5 v v oh_m p medium, high level output voltage i oh = ? 2ma v dd_hv_iox ? 0.8 ? v v ol_f p fast, low level output voltage i ol =11ma ? 0.5 v v oh_f p fast, high level output voltage i oh = ? 11 ma v dd_hv_iox ? 0.8 ? v i pu p equivalent pull-up current v in =v il ? 130 ? a v in =v ih ? ? 10 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ?130 i il p input leakage current (all bidirectional ports) t a = ? 40 to 125 c ? 1 a i il p input leakage current (all adc input-only ports) t a = ? 40 to 125 c ? 0.5 a c in d input capacitance ? ? 10 pf
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 51 3.10.4 input dc electrical characteristics definition figure 12 shows the dc electrical characteris tics behavior as function of time. figure 12. input dc electrical characteristics definition table 20. supply current (3.3 v, nvusro[pad3v5v] = 1) symbol c parameter conditions value 1 1 all values to be confirmed after characterization/data collection. unit typ max i dd_lv_corx t supply current run?maximum mode 2 2 maximum mode: flexpwm, adc, ctu, ds pi, linflex, flexcan, 15 output pins, pll_0 enabled, 125 c ambient. i/o supply current excluded. v dd_lv_corx externally forced at 1.3 v 40 mhz 44 55 ma 64 mhz 52 65 run?typical mode 3 3 typical mode configurations: dspi, li nflex, flexcan, 15 output pins, pll_ 0, 105 c ambient. i/o supply current excluded. 40 mhz 38 46 64 mhz 45 54 p halt mode 4 4 halt mode configurations: code fetched from sram, co de flash memory and data flash memory in low power mode, osc/pll_0 are off, core clock frozen, all peripherals disabled. ?1.510 stop mode 5 5 stop ?p? mode device under test (dut) configuration: code fetched from sram, code flash memory and data flash memory off, osc/pll_0 are off, core clock frozen, all peripherals disabled. ?110 i dd_adc tadc v dd_hv_adc0 at 3.3 v f adc =16mhz adc_0 3 4 i dd_osc t oscillator v dd_hv_osc at 3.3 v 8 mhz 2.6 3.2 v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0?
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 52 3.10.5 i/o pad current specification the i/o pads are distributed across the i/o supply segm ent. each i/o supply segm ent is associated to a v dd /v ss supply pair as described in table 21 . table 21. i/o supply segment package supply segment 12345 100 lqfp pin15?pin26 pin27?pin46 pin51?pin61 pin64?pin86 pin89?pin10 64 lqfp pin8?pin17 pin18?pin30 pin33?pin38 pin41?pin54 pin57?pin5 table 22. i/o consumption symbol c parameter conditions 1 value unit min typ max i swtslw ,2 cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed (2) cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst (2) cc d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??110ma v dd = 3.3 v 10%, pad3v5v = 1 ??50 i rmsslw cc d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed cc d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 53 3.11 main oscillator electrical characteristics the mpc5602p provides an oscillator/resonator driver. i rmsfst cc d root medium square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified 2 stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 23. main oscillator output electrical characteristics (5.0 v, nvusro[pad3v5v] = 0) symbol c parameter conditions value unit min max f osc sr ? oscillator frequency 4 40 mhz g m ? p transconductance 6.5 25 ma/v v osc ? t oscillation amplitude on xtal pin 1 ? v t oscsu ? t start-up time 1,2 1 the start-up time is dependent upon crystal char acteristics, board leakage, etc. high esr and excessive capacitive loads ca n cause long start-up time. 2 value captured when amplitude reaches 90% of xtal 8?ms c l cc t xtal load capacitance 3 3 this value is determined by the crystal manufact urer and board design. for 4 mhz to 40 mhz crystals specified for this oscillator, load capacitors should not exceed these limits. 4mhz 5 30 pf t8mhz526 t12mhz523 t16mhz519 t20mhz516 t40mhz58 table 22. i/o consumption (continued) symbol c parameter conditions 1 value unit min typ max
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 54 3.12 fmpll electrical characteristics table 24. main oscillator output electrical characteristics (3.3 v, nvusro[pad3v5v] = 1) symbol c parameter conditions value unit min max f osc sr ? oscillator frequency 4 40 mhz g m ? p transconductance 4 20 ma/v v osc ? t oscillation amplitude on xtal pin 1 ? v t oscsu ? t start-up time 1,2 1 the start-up time is dependent upon crystal char acteristics, board leakage, etc. high esr and excessive capacitive loads ca n cause long start-up time. 2 value captured when amplitude reaches 90% of xtal 8?ms c l cc t xtal load capacitance 3 3 this value is determined by the crystal manufact urer and board design. for 4 mhz to 40 mhz crystals specified for this oscillator, load capacitors should not exceed these limits. 4mhz 5 30 pf t8mhz526 t12mhz523 t16mhz519 t20mhz516 t40mhz58 table 25. input clock characteristics symbol parameter value unit min typ max f osc sr oscillator frequency 4 ? 40 mhz f clk sr frequency in bypass ? ? 64 mhz t rclk sr rise/fall time in bypass ? ? 1 ns t dc sr duty cycle 47.5 50 52.5 % table 26. fmpll electrical characteristics symbol c parameter conditions 1 value unit min max f ref_crystal f ref_ext d pll reference frequency range 2 crystal reference 4 40 mhz f pllin d phase detector input frequency range (after pre-divider) ?416mhz f fmpllout d clock frequency range in normal mode ? 16 64 mhz f free p free-running frequency measured using clock division?typically /16 20 150 mhz
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 55 t cyc d system clock period ? ? 1 / f sys ns f lorl d loss of reference frequency window 3 lower limit 1.6 3.7 mhz f lorh d upper limit 24 56 f scm d self-clocked mode frequency 4,5 ? 20 150 mhz c jitter t clkout period jitter 6,7,8,9 short-term jitter 10 f sys maximum ? 44%f clkout long-term jitter (average over 2 ms interval) f pllin =16mhz (resonator), f pllclk at 64 mhz, 4000 cycles ?10 ns t lpll d pll lock time 11, 12 ? ? 200 s t dc d duty cycle of reference ? 40 60 % f lck d frequency lock range ? ? 66%f sys f ul d frequency un-lock range ? ? 18 18 % f sys f cs d modulation depth center spread 0.25 4.0 13 %f sys f ds d down spread ? 0.5 ? 8.0 f mod d modulation frequency 14 ? ? 70 khz 1 v dd_lv_corx = 1.2 v 10%; v ss = 0 v; t a = ?40 to 125 c, unless otherwise specified 2 considering operation with pll not bypassed. 3 ?loss of reference frequency? window is the reference fre quency range outside of which the pll is in self clocked mode. 4 self clocked mode frequency is the frequency that the pll operates at when the reference frequency falls outside the f lor window. 5 f vco self clock range is 20?150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 6 this value is determined by the crystal manufacturer and board design. 7 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f sys . measurements are made with the device powered by filt ered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v dd_lv_cor0 and v ss_lv_cor0 and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 8 proper pc board layout procedures must be followed to achieve specifications. 9 values are obtained with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 10 short term jitter is measured on the clock rising edge at cycle n and cycle n+4. 11 this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this pll, load capacitors should not exceed these limits. 12 this specification applies to the period required for the pl l to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 13 this value is true when operating at frequencies above 60 mhz, otherwise f cs is 2% (above 64 mhz). 14 modulation depth will be attenuated from depth setting wh en operating at modulation frequencies above 50 khz. table 26. fmpll electrical characteristics (continued) symbol c parameter conditions 1 value unit min max
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 56 3.13 16 mhz rc oscillator electrical characteristics 3.14 analog-to-digital converter (adc) electrical characteristics the device provides a 10-bit successive approxima tion register (sar) analog-to-digital converter. table 27. 16 mhz rc oscillator electrical characteristics symbol c parameter conditions value unit min typ max f rc p rc oscillator frequency t a = 25 c ? 16 ? mhz ? rcmvar p fast internal rc oscillator variation over temperature and supply with respect to f rc at t a = 25 c in high-frequency configuration ? ? 5? 5%
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 57 figure 13. adc characteristics and error definitions 3.14.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high-frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenu ating the noise present on the input pin; it sources charge dur ing the sampling phase, when the analog signal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the source impedance valu e of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to th e adc conversion rate, it can be seen as a resistive path to (2) (1) (3) (4) (5) offset error (e o ) offset error (e o ) gain error (e g ) 1 lsb (ideal) 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve 1 lsb ideal = v dd_adc / 1024 v in(a) (lsb ideal ) code out
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 58 ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (fc c s ), where fc represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 equation 4 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 14. input equivalent circuit a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 14 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch closed). v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? r f c f r s r l r sw1 c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw1 : channel selection switch impedance r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 and c p2 ) c s : sampling capacitance
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 59 figure 15. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 5 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 ? a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 8 v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ?
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 60 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically desi gned to act as anti-aliasing. figure 16. spectral represe ntation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? = t s ? ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 61 eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 12 v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 62 3.14.2 adc conversion characteristics table 28. adc conversion characteristics symbol c parameter conditions 1 1 v dd = 3.3 v to 3.6 v / 4.5 v to 5.5 v, t a = ? 40 c to t a max , unless otherwise specified and analog input voltage from v ss_hv_adc0 to v dd_hv_adc0 . value unit min typ max f ck sr ? adc clock frequency (depends on adc configuration) (the duty cycle depends on adc clock 2 frequency) 2 ad_clk clock is always half of the adc module input cl ock defined via the auxiliary clock divider for the adc. ?3 3 3 when configured to allow 60 mhz adc, the minimum adc cl ock speed is 9 mhz, below which the precision is lost. ?60mhz f s sr ? sampling frequency ? ? ? 1.53 mhz t s ? d sampling time 4 4 during the sampling time the input capacitance c s can be charged/discharged by t he external source. the internal resistance of the analog source must allow the ca pacitance to reach its final voltage level within t s . after the end of the sampling time t s , changes of the analog input voltage have no ef fect on the conversion result. values for the sample clock t s depend on programming. f adc = 20 mhz, inpsamp = 3 125 ? ? ns f adc = 9 mhz, inpsamp = 255 ? ? 28.2 s t c ? p conversion time 5 5 this parameter include s the sampling time t s . f adc = 20 mhz 6 , inpcmp = 1 0.650 ? ? s t adc_pu sr ? adc power-up delay (time needed for adc to settle exiting from software power down; pwdn bit = 0) ???1.5s c s 7 ? d adc input sampling capacitance ? ? ? 2.5 pf c p1 7 ? d adc input pin capacitance 1 ? ? ? 3 pf c p2 7 ? d adc input pin capacitance 2 ? ? ? 1 pf r sw1 7 ? d internal resistance of analog source v dd_hv_adc0 = 5 v 10% ? ? 0.6 k ? v dd_hv_adc0 = 3.3 v 10% ? ? 3 k ? r ad 7 ? d internal resistance of analog source ? ? ? 2 k ? i inj ? t input current injection cur rent injection on one adc input, different from the converted one. remains within tue specification ? 5? 5ma inl cc p integral non-linearity no overload ? 1.5 ? 1.5 lsb dnl cc p differential non-linearity no overload ? 1.0 ? 1.0 lsb e o cc t offset error ? ? 1 ? lsb e g cc t gain error ? ? 1 ? lsb tue cc p total unadjusted error without current injection ? ? 2.5 ? 2.5 lsb tue cc t total unadjusted error with current injection ? ? 3? 3lsb
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 63 3.15 flash memory electrical characteristics 3.15.1 program/erase characteristics 6 20 mhz adc clock. specific prescaler is programmed on mc_pll_clk to provide 20 mhz clock to the adc. 7 see figure 14 . table 29. program and erase specifications symbol c parameter value unit min typ 1 1 typical program and erase times assume nominal supply va lues and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/eras e cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the sp ecified number of program/er ase cycles. these maximum values are characterized but not guaranteed. t wprogram p word program time for data flash memory 4 4 actual hardware programming times. this does not include software overhead. ? 30 70 500 s t dwprogram p double word program time for code flash memory 4 ? 22 50 500 s t bkprg p bank program (256 kb) 4,5 5 typical bank programming time assumes that all cells are programmed in a single pulse. in reality some cells will require more than one pulse, adding a small overhead to total bank programming time (see ?initial max? column). ? 0.73 0.83 17.5 s p bank program (64 kb) 4,5 ?0.491.24.1s t 16kpperase p 16 kb block pre-program and erase time for code flash memory ? 300 500 5000 ms 16 kb block pre-program and erase time for data flash memory ? 700 800 5000 t 32kpperase p 32 kb block pre-program and erase time ? 400 600 5000 ms t 128kpperase p 128 kb block pre-program and erase time ? 800 1300 7500 ms
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 64 3.15.2 flash memory power supply dc characteristics table 32 shows the power supply dc char acteristics on external supply. table 30. flash memory module life symbol c parameter conditions value unit min typ p/e c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100,000 ? cycles p/e c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10,000 100,000 cycles p/e c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1,000 100,000 cycles retention c minimum data retention at 85 c average ambient temperature 1 1 ambient temperature averaged over duration of applic ation, not to exceed recommended product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? years blocks with 10,000 p/e cycles 10 ? years blocks with 100,000 p/e cycles 5 ? years table 31. flash memory read access timing symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified max value unit f max c maximum working frequency for code flash memory at given number of wait states in worst conditions 2 wait states 66 mhz 0 wait states 18 f max c maximum working frequency for data flash memory at given number of wait states in worst conditions 8 wait states 66 mhz table 32. flash memory power supply dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max i flpw cc d sum of the current consumption on v dd_hv_iox and v dd_lv_corx during low-power mode code flash memory ? ? 900 a i fpwd cc d sum of the current consumption on v dd_hv_iox and v dd_lv_corx during power-down mode code flash memory ? ? 150 a data flash memory ? ? 150
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 65 3.15.3 start-up/switch-off timings 3.16 ac specifications 3.16.1 pad ac specifications table 33. start-up time/switch-off time symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max t flarstexit cc t delay for flash module to exit reset mode code flash memory ? ? 125 s t data flash memory ? ? 125 t flalpexit cc d delay for flash module to exit low-power mode code flash memory ? ? 0.5 t flapdexit cc t delay for flash module to exit power-down mode code flash memory ? ? 30 t data flash memory ? ? 30 t flalpentry cc d delay for flash module to enter low-power mode code flash memory ? ? 0.5 table 34. output pin transition times symbol c parameter conditions 1 value unit min typ max t tr cc d output transition time output pin 2 slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ? ? 50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??40 tc l = 50 pf ? ? 50 dc l = 100 pf ? ? 75 t tr cc d output transition time output pin 2 medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ? ? 10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 66 figure 17. pad output delay 3.17 ac timing characteristics 3.17.1 reset pin characteristics the mpc5602p implements a dedicated bidirectional reset pin. t tr cc d output transition time output pin 2 fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 t sym 3 cc t symmetric transition time, same drive strength between n and p transistor v dd = 5.0 v 10%, pad3v5v = 0 ? ? 4 ns v dd = 3.3 v 10%, pad3v5v = 1 ? ? 5 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 c to t a max , unless otherwise specified. 2 c l includes device and package capacitances (c pkg < 5 pf). 3 transition timing of both positive and negative slopes will differ maximum 50%. table 34. output pin transition times (continued) symbol c parameter conditions 1 value unit min typ max v dd_hv_iox /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 67 figure 18. start-up reset requirements figure 19. noise filtering on reset signal v il v dd device reset forced by v reset v ddmin v reset v ih device start-up phase t por v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 68 table 35. reset electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v ih sr p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol cc p output low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 3 3 this is a transient configuration duri ng power-up, up to the e nd of reset phase2 (refer to rgm module section of device reference manual). ? ? 0.1v dd push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc d output transition time output pin 4 medium configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??10ns c l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 c l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 c l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 c l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 c l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst sr p reset input filtered pulse ???40ns w nfrst sr p reset input not filtered pulse ? 500 ? ? ns t por cc d maximum delay before internal reset is released after all v dd_hv reach nominal supply monotonic v dd_hv supply ramp ? ? 1 ms |i wpu | cc p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 5 10 ? 250
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 69 3.17.2 ieee 1149.1 interface timing figure 20. jtag test clock input timing 4 c l includes device and package capacitance (c pkg <5pf). 5 the configuration pad3v5 = 1 when v dd = 5 v is only transient co nfiguration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are config ured in input or in high impedance state. table 36. jtag pin ac electrical characteristics no. symbol c parameter conditions value unit min max 1t jcyc cc d tck cycle time ? 100 ? ns 2t jdc cc d tck clock pulse width (measured at v dd_hv_iox /2) ? 40 60 ns 3t tckrise cc d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis cc d tms, tdi data setup time ? 5 ? ns 5t tmsh, t tdih cc d tms, tdi data hold time ? 25 ? ns 6t tdov cc d tck low to tdo data valid ? ? 40 ns 7t tdoi cc d tck low to tdo data invalid ? 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 40 ? ns 9t bsdv cc d tck falling edge to output valid ? ? 50 ns 10 t bsdvz cc d tck falling edge to output valid out of high impedance ??50ns 11 t bsdhz cc d tck falling edge to output high impedance ? ? 50 ns 12 t bsdst cc d boundary scan input valid to tck rising edge ? 50 ? ns 13 t bsdht cc d tck rising edge to boundary scan input invalid ? 50 ? ns tck 1 2 2 3 3
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 70 figure 21. jtag test access port timing tck 4 5 6 7 8 tms, tdi tdo
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 71 figure 22. jtag boundary scan timing 3.17.3 nexus timing table 37. nexus debug port timing 1 no. symbol c parameter value unit min typ max 1t tcyc cc d tck cycle time 4 2 ??t cyc 2t ntdis cc d tdi data setup time 5 ? ? ns t ntmss cc d tms data setup time 5 ? ? ns 3t ntdih cc d tdi data hold time 25 ? ? ns t ntmsh cc d tms data hold time 25 ? ? ns 4t tdov cc d tck low to tdo data valid 10 ? 20 ns 5t tdoi cc d tck low to tdo data invalid ? ? ? ns tck output signals input signals output signals 11 12 13 14 15
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 72 figure 23. nexus output timing figure 24. nexus event trigger and test clock timing 1 all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. 2 lower frequency is required to be fully compliant to standard. 1 3 4 mcko mdo mseo evto output data valid 2 tck 5 evti evto
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 73 figure 25. nexus tdi, tms, tdo timing 3.17.4 external interrupt timing (irq pin) table 38. external interrupt timing 1 1 irq timing specified at f sys = 64 mhz and v dd_hv_iox = 3.0 v to 5.5 v, t a =t l to t h , and c l = 200 pf with src = 0b00 no. symbol c parameter conditions value unit min max 1t ipwl cc d irq pulse width low ? 4 ? t cyc 2t ipwh cc d irq pulse width high ? 4 ? t cyc 3t icyc cc d irq edge to edge time 2 2 applies when irq pins are configured for rising edge or falling edge events, but not both. ?4+n 3 3 n = isr time to clear the flag ?t cyc tdo 6 7 tms, tdi 8 tck 9
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 74 figure 26. external interrupt timing 3.17.5 dspi timing table 39. dspi timing 1 no. symbol c parameter conditions value unit min max 1t sck cc d dspi cycle time master (mtfe = 0) 60 ? ns slave (mtfe = 0) 60 ? 2t csc cc d cs to sck delay ? 16 ? ns 3t asc cc d after sck delay ? 26 ? ns 4t sdc cc d sck duty cycle ? 0.4 * t sck 0.6 * t sck ns 5t a cc d slave access time ss active to sout valid ? 30 ns 6t dis cc d slave sout disable time ss inactive to sout high impedance or invalid ? 16 ns 7t pcsc cc d pcsx to pcss time ? 13 ? ns 8t pasc cc d pcss to pcsx time ? 13 ? ns 9t sui cc d data setup time for inputs master (mtfe = 0) 35 ? ns slave 4? master (mtfe = 1, cpha = 0) 35 ? master (mtfe = 1, cpha = 1) 35 ? 10 t hi cc d data hold time for inputs master (mtfe = 0) ? 5 ?ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ? 5? irq 2 3 1
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 75 figure 27. dspi classic spi timing ? master, cpha = 0 11 t suo cc d data valid (after sck edge) master (mtfe = 0) ? 12 ns slave ? 36 master (mtfe = 1, cpha = 0) ? 12 master (mtfe = 1, cpha = 1) ? 12 12 t ho cc d data hold time for outputs master (mtfe = 0) ? 2?ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ? 2? 1 all timing are provided with 50 pf capacitance on output, 1 ns transition time on input signal table 39. dspi timing 1 (continued) no. symbol c parameter conditions value unit min max data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 note : numbers shown reference ta b l e 3 9 .
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 76 figure 28. dspi classic spi timing ? master, cpha = 1 figure 29. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) note : numbers shown reference ta b l e 3 9 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) note : numbers shown reference table 39 .
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 77 figure 30. dspi classic spi timing ? slave, cpha = 1 figure 31. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note : numbers shown reference ta b l e 3 9 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) note : numbers shown reference table 39 .
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 78 figure 32. dspi modified transfer format timing ? master, cpha = 1 figure 33. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) note : numbers shown reference ta b l e 3 9 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 note : numbers shown reference table 39 .
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 79 figure 34. dspi modified transfer format timing ? slave, cpha = 1 figure 35. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note : numbers shown reference table 39 . pcsx 7 8 pcss note : numbers shown reference table 39 .
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 80 4 package characteristics 4.1 package mechanical data 4.1.1 100 lqfp mechanical outline drawing
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 81 figure 36. 100 lqfp package mechanical drawing (part 1)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 82 figure 37. 100 lqfp package mechanical drawing (part 2)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 83 figure 38. 100 lqfp package mechanical drawing (part 3)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 84 4.1.2 64 lqfp mechanical outline drawing figure 39. 64 lqfp package mechanical drawing (part 1)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 85 figure 40. 64lqfp package mechanical drawing (part 2)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 86 figure 41. 64lqfp package mechanical drawing (part 3)
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 87 5 ordering information figure 42. commercial product code structure qualification status power architecture core automotive platform core version flash size (core dependent) product optional fields mpc56 pef0 m example code: 02 temperature spec. package code qualification status m = mc status s = automotive qualified p = pc status automotive platform 56 = power architecture in 90 nm core version 0 = e200z0 flash size (z0 core) 1 = 192 kb 2 = 256 kb product p = mpc560xp family optional fields e = data flash (blank if none) frequency ll temperature spec. v = ?40 to 105 c m = ?40 to 125 c package code lh = 64 lqfp ll = 100 lqfp frequency 4 = 40 mhz 6= 64mhz fab & mask revision r = tape & reel (blank if tray) 4r
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 88 6 document revision history table 40 summarizes revisions to this document. table 40. revision history revision date description of 1 05 aug 2009 initial release. 2 07 apr 2010 editorial updates updated the following items in the ?mpc5602p device comparison? table: ? the heading ? the ?sram? row ? the ?flexcan? row ? the ?ctu? row ? the ?flexpwm? row ? the ?linflex? row ? the ?dspi? row ? the ?nexus? row ? deleted the footnote no. 3 added the ?wakeup unit? block in the mpc5602p block diagram updated the ?absolute maximum ratings? table updated the ?recommended operating conditions (5.0 v)? table updated the ?recommended operating conditions (3.3 v)? table updated the ?thermal characterist ics for 100-pin lqfp? table: ? ? jt : changed the typical value updated the ?emi testing specif ications? table: replaced all values in ?level (max)? column with tbd updated the ?electrical ch aracteristics? section: ? added the ?introduction? section ? added the ?parameter classification? section ? added the ?nvusro register? section ? added the ?power supplies constraints (?0.3 v ? v dd_hv_iox ? 6.0 v)? figure ? added the ?independent adc supply (?0.3 v ? v dd_hv_reg ? 6.0 v)? figure ? added the ?power supplies constraints (3.0 v ? v dd_hv_iox ? 5.5 v)? figure ? added the ?independent adc supply (3.0 v ? v dd_hv_reg ? 5.5 v)? figure updated the ?power management electr ical characteristics? section updated the ?power up/down sequencing? section updated the ?dc electrical characteristics? section ? deleted the ?nvusro register? section ? updated the ?dc electrical characterist ics (5.0 v, nvusro[pad3v5v] = 0)? section: ? deleted all rows concerning reset ? deleted ?i vpp ? row ? added the max value for c in ? updated the ?dc electrical characterist ics (3.3 v, nvusro[pad3v5v] = 0)? section: ? deleted all rows concerning reset ? deleted ?i vpp ? row ? added the max value for c in added the ?i/o pad current specification? section updated the orderable part number summarytable. 2 (continued) 07 apr 2010 added ?appendix a?
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 89 3 16 dec 2010 ?introduction? section: ? changed title (was ?overview?) ? updated contents ?mpc5602p device comparison? table: ? added sentence above table ? removed ?flexray? row ?mpc5602p block diagram?: added the following blocks: mc_cgm, mc_me, mc_pcu, mc_rgm, crc, and sscm added ?mpc5602p series block summary? table ?pin muxing? section: removed in formation on ?symmetric pads? ?electrical characte ristics? section: ? updated ?caution? note ? demoted ?nvusro register? section to subs ection of ?dc electrical characteristics? section ? ?nvusro register? section: deleted ?nvusro[watchdog_en] field description? section updated ?emi testing specifications? table ?low voltage monitor electrical c haracteristics? table: updated v mlvddok_h max value ?dc electrical characteristics (5.0 v, nvusro[pad3v5v] = 0)? table: removed vol_sym , and v oh_sym rows ?supply current (5.0 v, nvusro[pad3v5v] = 0)? table: ?i dd_lv_core , run?maximum mode, 40/64 mh z: updated typ/max values ?i dd_lv_core , run?airbag mode, 40/64 mhz: updated typ/max values ?i dd_lv_core , run?maximum mode, ?p? parameter classification: removed ?i dd_flash : removed rows ?i dd_adc , maximum mode: updated typ/max values ?i dd_osc : updated max value updated ?dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1)? table ?supply current (3.3 v, nvusro[pad3v5v] = 1)? table: ?i dd_lv_core , run?maximum mode, 40/64 mh z: updated typ/max values ?i dd_lv_core , run?airbag mode, 40/64 mhz: updated typ/max values ?i dd_flash : removed rows ?i dd_adc , maximum mode: updated typ/max values ?i dd_osc : updated max value added ?i/o consumption? table removed ?i/o weight? table updated ?main oscillator electrical characteri stics (5.0 v, nvusro[pad3v5v] = 0)? table updated ?main oscillator electrical characteri stics (3.3 v, nvusro[pad3v5v] = 1)? table ?input clock characteristics? table: updated f clk max value ?pllmrfm electrical specifications (v ddpll = 1.08 v to 1.32 v, v ss = v sspll = 0 v, t a =t l to t h )? table: ? updated supply voltage range for v ddpll in the table title ? updated f scm max value ? updated c jitter row ? updated f mod max value updated ?16 mhz rc oscillator electrical characteristics? table updated ?adc conversion characteristics? table table 40. revision history (continued) revision date description of
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 90 3 (continued) 16 dec 2010 ?program and erase specifications? table: ?t wprogram : updated initial max and max values ?t bkprg , 64 kb: updated initial max and max values ? added information about ?erase time? for data flash ?flash module life? table: ? p/e, 32 kb: added typ value ? p/e, 128 kb: added typ value replaced ?pad ac specifications (5.0 v, nvusro[pad3v5v] = 0)? and ?pad ac specifications (3.3 v, invusro[pad3v5v] = 1)? tables with ?output pin transition times? table ?jtag pin ac electrical characteristics? table: ?t tdov : updated max value ?t tdohz : added min value and removed max value ?nexus debug port timing? table: removed the rows ?t mcyc ?, ?t mdov ?, ?t mseov ?, and ?t evtov ? updated ?external interrupt timing (irq pin)? table updated ?flexcan timing? table updated ?dspi timing? table updated ?ordering information? section table 40. revision history (continued) revision date description of
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 91 4 11 may 2011 editorial and formatting changes throughout section 1, ?introduction : reorganized contents mpc5602p block diagram: reorganized bloc ks above and below peripheral bridge; made arrow going from peripheral bridge to crossbar switch bidirectional updated section 1.5, ?feature list : ? changed core feature from ?64 mhz? to ?up to 64 mhz? ? memory organization ? moved ?16-channel edma controlle r? item to ?interrupts and events? item ? linflex: changed ?2 linflex modules? to ?up to 2 linflex modules? ? dspi: changed ?3 dspi channels? to ?up to 3 dspi channels? ? adc: changed ?16 input channels? to ?up to 16 input channels? added section 1.5, ?feature details 64-pin and 100-pin lqfp pinout diagra ms: replaced instances of hv_ad0 with hv_adc0 system pins: updated ?xtal? and ?extal? rows updated lqfp thermal characteristics updated emi testing specifications section 3.8.1, ?voltage regulato r electrical characteristics : removed bcp56 from named bjts; replaced two configuration diagrams and two electrical characteristics tables with single diagram and single table voltage regulator electrical characteristics: updated v dd_lv_regcor row low voltage monitor electrical characteristics: updated v mlvddok_h max value?was 1.15 v; is 1.145 v supply current (5.0 v, nvusro[pad3v5v] = 0): changed symbol i dd_lv_core to i dd_lv_corx ; changed parameter classification from t to p for i dd_lv_corx run?maximum mode at 64 mhz; added i dd_flash characteristics; replaced instances of ?airbag? mode with ?typical mode? supply current (3.3 v, nvusro[pad3v5v] = 1): changed symbol i dd_lv_core to i dd_lv_corx ; replaced instances of ?airbag? mode with ?typical mode? dc electrical characteristics (3.3 v, nvusro[pad3v5v] = 1): corrected parameter description for v ol_f ?was ?fast, high level output voltage?; is ?fast, low level output voltage? added section 3.10.4, ?input dc electrical characteristics definition main oscillator output electrical characterist ics tables: replaced instances of extal with xtal; added load capacitance parameter fmpll electrical characteristics: updat ed conditions and table title; removed f sys row; updated f fmpllout values; replaced instances of v ddpll with v dd_lv_cor0 ; replaced instances of v sspll with v ss_lv_cor0 16 mhz rc oscillator electrical characteristics: removed rows ? rcmtrim and ? rcmstep adc characteristics and error definitions: updated symbols adc conversion characteristics: updated symbols; added row t adc_pu added section 3.15.2, ?flash memory power supply dc characteristics added section 3.15.3, ?start- up/switch-off timings removed section ?generic timing diagrams? 4 (cont?d) 11 may 2011 updated start-up reset requirements diagram removed flexcan timi ng characteristics reset electrical characteristics: added row for t por in the range of figures ?dspi classic spi timing ? master, cpha = 0? to ?dspi pcs strobe (pcss) timing?: added note ta b l e a - 1 : added ?dut?, ?npn?, and ?risc? table 40. revision history (continued) revision date description of
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 92 4.1 15 sep 2011 deleted the ?freescale confidential proprietary, nda required? label (the document is public). table 40. revision history (continued) revision date description of
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 93 appendix a abbreviations table a-1 lists abbreviations used in this document. table a-1. abbreviations abbreviation meaning cmos complementary metal?oxide?semiconductor cpha clock phase cpol clock polarity cs peripheral chip select dut device under test ecc error code correction evto event out gpio general purpose input / output mc modulus counter mcko message clock out mcu microcontroller unit mdo message data out mseo message start/end out mtfe modified timing format enable npn negative-positive-negative nvusro non-volatile user options register ptf post trimming frequency pwm pulse width modulation risc reduced instru ction set computer sck serial communications clock sout serial data out tbc to be confirmed tbd to be defined tck test clock input tdi test data input tdo test data output tms test mode select
mpc5602p microcontroller data sheet, rev. 4.1 freescale semiconductor 94
document number: mpc5602p rev. 4.1 09/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc. 2010-2011. all rights reserved.

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